1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2007 Freescale Semiconductor, Inc. 4 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com 5 * 6 * This files is mostly identical to the original from 7 * board/freescale/mpc8308rdb/sdram.c 8 */ 9 10 #include <common.h> 11 #include <mpc83xx.h> 12 13 #include <asm/bitops.h> 14 #include <asm/io.h> 15 16 #include <asm/processor.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 /* Fixed sdram init -- doesn't use serial presence detect. 21 * 22 * This is useful for faster booting in configs where the RAM is unlikely 23 * to be changed, or for things like NAND booting where space is tight. 24 */ 25 static long fixed_sdram(void) 26 { 27 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 28 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; 29 u32 msize_log2 = __ilog2(msize); 30 31 out_be32(&im->sysconf.ddrlaw[0].bar, 32 CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000); 33 out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); 34 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); 35 36 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); 37 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); 38 39 /* Currently we use only one CS, so disable the other bank. */ 40 out_be32(&im->ddr.cs_config[1], 0); 41 42 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); 43 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); 44 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); 45 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); 46 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); 47 48 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); 49 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); 50 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); 51 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); 52 53 out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); 54 sync(); 55 56 /* enable DDR controller */ 57 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); 58 sync(); 59 60 return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize); 61 } 62 63 int dram_init(void) 64 { 65 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 66 u32 msize; 67 68 if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im) 69 return -1; 70 71 /* DDR SDRAM */ 72 msize = fixed_sdram(); 73 74 /* set total bus SDRAM size(bytes) -- DDR */ 75 gd->ram_size = msize; 76 77 return 0; 78 } 79