1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com 4 * 5 * This files is mostly identical to the original from 6 * board/freescale/mpc8308rdb/sdram.c 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <mpc83xx.h> 13 14 #include <asm/bitops.h> 15 #include <asm/io.h> 16 17 #include <asm/processor.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 /* Fixed sdram init -- doesn't use serial presence detect. 22 * 23 * This is useful for faster booting in configs where the RAM is unlikely 24 * to be changed, or for things like NAND booting where space is tight. 25 */ 26 static long fixed_sdram(void) 27 { 28 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 29 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; 30 u32 msize_log2 = __ilog2(msize); 31 32 out_be32(&im->sysconf.ddrlaw[0].bar, 33 CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000); 34 out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); 35 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); 36 37 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); 38 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); 39 40 /* Currently we use only one CS, so disable the other bank. */ 41 out_be32(&im->ddr.cs_config[1], 0); 42 43 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); 44 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); 45 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); 46 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); 47 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); 48 49 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); 50 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); 51 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); 52 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); 53 54 out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); 55 sync(); 56 57 /* enable DDR controller */ 58 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); 59 sync(); 60 61 return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize); 62 } 63 64 int dram_init(void) 65 { 66 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 67 u32 msize; 68 69 if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im) 70 return -1; 71 72 /* DDR SDRAM */ 73 msize = fixed_sdram(); 74 75 /* set total bus SDRAM size(bytes) -- DDR */ 76 gd->ram_size = msize; 77 78 return 0; 79 } 80