1 /* 2 * Board functions for mini-box PICOSAM9G45 (AT91SAM9G45) based board 3 * (C) Copyright 2015 Inter Act B.V. 4 * 5 * Based on: 6 * U-Boot file: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c 7 * (C) Copyright 2007-2008 8 * Stelian Pop <stelian@popies.net> 9 * Lead Tech Design <www.leadtechdesign.com> 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #include <common.h> 15 #include <asm/io.h> 16 #include <asm/arch/clk.h> 17 #include <asm/arch/at91sam9g45_matrix.h> 18 #include <asm/arch/at91sam9_smc.h> 19 #include <asm/arch/at91_common.h> 20 #include <asm/arch/gpio.h> 21 #include <asm/arch/clk.h> 22 #include <lcd.h> 23 #include <linux/mtd/rawnand.h> 24 #include <atmel_lcdc.h> 25 #include <atmel_mci.h> 26 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) 27 #include <net.h> 28 #endif 29 #include <netdev.h> 30 #include <asm/mach-types.h> 31 32 DECLARE_GLOBAL_DATA_PTR; 33 34 /* ------------------------------------------------------------------------- */ 35 /* 36 * Miscelaneous platform dependent initialisations 37 */ 38 39 #if defined(CONFIG_SPL_BUILD) 40 #include <spl.h> 41 42 void at91_spl_board_init(void) 43 { 44 #ifdef CONFIG_SYS_USE_MMC 45 at91_mci_hw_init(); 46 #endif 47 } 48 49 #include <asm/arch/atmel_mpddrc.h> 50 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) 51 { 52 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); 53 54 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 55 ATMEL_MPDDRC_CR_NR_ROW_14 | 56 ATMEL_MPDDRC_CR_DQMS_SHARED | 57 ATMEL_MPDDRC_CR_CAS_DDR_CAS3); 58 59 ddr2->rtr = 0x24b; 60 61 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */ 62 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */ 63 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */ 64 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */ 65 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */ 66 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/ 67 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */ 68 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */ 69 70 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */ 71 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | 72 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | 73 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); 74 75 ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | 76 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | 77 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | 78 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); 79 } 80 81 void mem_init(void) 82 { 83 struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX; 84 struct atmel_mpddrc_config ddr2; 85 unsigned long csa; 86 87 ddr2_conf(&ddr2); 88 89 at91_system_clk_enable(AT91_PMC_DDR); 90 91 /* Chip select 1 is for DDR2/SDRAM */ 92 csa = readl(&mat->ebicsa); 93 csa |= AT91_MATRIX_EBI_CS1A_SDRAMC; 94 csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V; 95 writel(csa, &mat->ebicsa); 96 97 /* DDRAM2 Controller initialize */ 98 ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2); 99 ddr2_init(ATMEL_BASE_DDRSDRC1, ATMEL_BASE_CS1, &ddr2); 100 } 101 #endif 102 103 #ifdef CONFIG_CMD_USB 104 static void picosam9g45_usb_hw_init(void) 105 { 106 at91_periph_clk_enable(ATMEL_ID_PIODE); 107 108 at91_set_gpio_output(AT91_PIN_PD1, 0); 109 at91_set_gpio_output(AT91_PIN_PD3, 0); 110 } 111 #endif 112 113 #ifdef CONFIG_MACB 114 static void picosam9g45_macb_hw_init(void) 115 { 116 struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; 117 118 at91_periph_clk_enable(ATMEL_ID_EMAC); 119 120 /* 121 * Disable pull-up on: 122 * RXDV (PA15) => PHY normal mode (not Test mode) 123 * ERX0 (PA12) => PHY ADDR0 124 * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0 125 * 126 * PHY has internal pull-down 127 */ 128 writel(pin_to_mask(AT91_PIN_PA15) | 129 pin_to_mask(AT91_PIN_PA12) | 130 pin_to_mask(AT91_PIN_PA13), 131 &pioa->pudr); 132 133 at91_phy_reset(); 134 135 /* Re-enable pull-up */ 136 writel(pin_to_mask(AT91_PIN_PA15) | 137 pin_to_mask(AT91_PIN_PA12) | 138 pin_to_mask(AT91_PIN_PA13), 139 &pioa->puer); 140 141 /* And the pins. */ 142 at91_macb_hw_init(); 143 } 144 #endif 145 146 #ifdef CONFIG_LCD 147 148 vidinfo_t panel_info = { 149 .vl_col = 480, 150 .vl_row = 272, 151 .vl_clk = 9000000, 152 .vl_sync = ATMEL_LCDC_INVLINE_NORMAL | 153 ATMEL_LCDC_INVFRAME_NORMAL, 154 .vl_bpix = 3, 155 .vl_tft = 1, 156 .vl_hsync_len = 45, 157 .vl_left_margin = 1, 158 .vl_right_margin = 1, 159 .vl_vsync_len = 1, 160 .vl_upper_margin = 40, 161 .vl_lower_margin = 1, 162 .mmio = ATMEL_BASE_LCDC, 163 }; 164 165 166 void lcd_enable(void) 167 { 168 at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */ 169 } 170 171 void lcd_disable(void) 172 { 173 at91_set_A_periph(AT91_PIN_PE6, 0); /* power down */ 174 } 175 176 static void picosam9g45_lcd_hw_init(void) 177 { 178 at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */ 179 at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */ 180 at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */ 181 at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */ 182 at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */ 183 184 at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */ 185 at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */ 186 at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */ 187 at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */ 188 at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */ 189 at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */ 190 at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */ 191 at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */ 192 at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */ 193 at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */ 194 at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */ 195 at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */ 196 at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */ 197 at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */ 198 at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */ 199 at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */ 200 at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */ 201 at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */ 202 at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */ 203 at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */ 204 at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */ 205 at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */ 206 at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */ 207 at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */ 208 209 at91_periph_clk_enable(ATMEL_ID_LCDC); 210 211 gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE; 212 } 213 214 #ifdef CONFIG_LCD_INFO 215 #include <nand.h> 216 #include <version.h> 217 218 void lcd_show_board_info(void) 219 { 220 ulong dram_size; 221 int i; 222 char temp[32]; 223 224 lcd_printf("%s\n", U_BOOT_VERSION); 225 lcd_printf("(C) 2015 Inter Act B.V.\n"); 226 lcd_printf("support@interact.nl\n"); 227 lcd_printf("%s CPU at %s MHz\n", 228 ATMEL_CPU_NAME, 229 strmhz(temp, get_cpu_clk_rate())); 230 231 dram_size = 0; 232 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 233 dram_size += gd->bd->bi_dram[i].size; 234 lcd_printf(" %ld MB SDRAM\n", dram_size >> 20); 235 } 236 #endif /* CONFIG_LCD_INFO */ 237 #endif 238 239 #ifdef CONFIG_GENERIC_ATMEL_MCI 240 int board_mmc_init(bd_t *bis) 241 { 242 at91_mci_hw_init(); 243 244 return atmel_mci_init((void *)ATMEL_BASE_MCI0); 245 } 246 #endif 247 248 int board_early_init_f(void) 249 { 250 at91_seriald_hw_init(); 251 return 0; 252 } 253 254 int board_init(void) 255 { 256 gd->bd->bi_arch_number = MACH_TYPE_PICOSAM9G45; 257 258 /* adress of boot parameters */ 259 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 260 261 #ifdef CONFIG_CMD_USB 262 picosam9g45_usb_hw_init(); 263 #endif 264 #ifdef CONFIG_ATMEL_SPI 265 at91_spi0_hw_init(1 << 4); 266 #endif 267 #ifdef CONFIG_MACB 268 picosam9g45_macb_hw_init(); 269 #endif 270 #ifdef CONFIG_LCD 271 picosam9g45_lcd_hw_init(); 272 #endif 273 return 0; 274 } 275 276 int dram_init(void) 277 { 278 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) 279 + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); 280 281 return 0; 282 } 283 284 int dram_init_banksize(void) 285 { 286 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 287 gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, 288 PHYS_SDRAM_1_SIZE); 289 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 290 gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, 291 PHYS_SDRAM_2_SIZE); 292 293 return 0; 294 } 295 296 #ifdef CONFIG_RESET_PHY_R 297 void reset_phy(void) 298 { 299 } 300 #endif 301 302 int board_eth_init(bd_t *bis) 303 { 304 int rc = 0; 305 #ifdef CONFIG_MACB 306 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); 307 #endif 308 return rc; 309 } 310 311 /* SPI chip select control */ 312 #ifdef CONFIG_ATMEL_SPI 313 #include <spi.h> 314 315 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 316 { 317 return bus == 0 && cs < 2; 318 } 319 320 void spi_cs_activate(struct spi_slave *slave) 321 { 322 switch (slave->cs) { 323 case 1: 324 at91_set_gpio_output(AT91_PIN_PB18, 0); 325 break; 326 case 0: 327 default: 328 at91_set_gpio_output(AT91_PIN_PB3, 0); 329 break; 330 } 331 } 332 333 void spi_cs_deactivate(struct spi_slave *slave) 334 { 335 switch (slave->cs) { 336 case 1: 337 at91_set_gpio_output(AT91_PIN_PB18, 1); 338 break; 339 case 0: 340 default: 341 at91_set_gpio_output(AT91_PIN_PB3, 1); 342 break; 343 } 344 } 345 #endif /* CONFIG_ATMEL_SPI */ 346