1 /*
2  * Board functions for mini-box PICOSAM9G45 (AT91SAM9G45) based board
3  * (C) Copyright 2015 Inter Act B.V.
4  *
5  * Based on:
6  * U-Boot file: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
7  * (C) Copyright 2007-2008
8  * Stelian Pop <stelian@popies.net>
9  * Lead Tech Design <www.leadtechdesign.com>
10  *
11  * SPDX-License-Identifier:	GPL-2.0+
12  */
13 
14 #include <common.h>
15 #include <asm/io.h>
16 #include <asm/arch/clk.h>
17 #include <asm/arch/at91sam9g45_matrix.h>
18 #include <asm/arch/at91sam9_smc.h>
19 #include <asm/arch/at91_common.h>
20 #include <asm/arch/gpio.h>
21 #include <asm/arch/clk.h>
22 #include <lcd.h>
23 #include <linux/mtd/nand.h>
24 #include <atmel_lcdc.h>
25 #include <atmel_mci.h>
26 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
27 #include <net.h>
28 #endif
29 #include <netdev.h>
30 
31 DECLARE_GLOBAL_DATA_PTR;
32 
33 /* ------------------------------------------------------------------------- */
34 /*
35  * Miscelaneous platform dependent initialisations
36  */
37 
38 #if defined(CONFIG_SPL_BUILD)
39 #include <spl.h>
40 
41 void at91_spl_board_init(void)
42 {
43 #ifdef CONFIG_SYS_USE_MMC
44 	at91_mci_hw_init();
45 #endif
46 }
47 
48 #include <asm/arch/atmel_mpddrc.h>
49 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
50 {
51 	ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
52 
53 	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
54 		    ATMEL_MPDDRC_CR_NR_ROW_14 |
55 		    ATMEL_MPDDRC_CR_DQMS_SHARED |
56 		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
57 
58 	ddr2->rtr = 0x24b;
59 
60 	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
61 		      2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
62 		      2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
63 		      8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */
64 		      2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
65 		      1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
66 		      1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
67 		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
68 
69 	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
70 		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
71 		      16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
72 		      14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
73 
74 	ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
75 		      0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
76 		      7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
77 		      2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
78 }
79 
80 void mem_init(void)
81 {
82 	struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
83 	struct atmel_mpddrc_config ddr2;
84 	unsigned long csa;
85 
86 	ddr2_conf(&ddr2);
87 
88 	at91_system_clk_enable(AT91_PMC_DDR);
89 
90 	/* Chip select 1 is for DDR2/SDRAM */
91 	csa = readl(&mat->ebicsa);
92 	csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
93 	csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V;
94 	writel(csa, &mat->ebicsa);
95 
96 	/* DDRAM2 Controller initialize */
97 	ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
98 	ddr2_init(ATMEL_BASE_DDRSDRC1, ATMEL_BASE_CS1, &ddr2);
99 }
100 #endif
101 
102 #ifdef CONFIG_CMD_USB
103 static void picosam9g45_usb_hw_init(void)
104 {
105 	at91_periph_clk_enable(ATMEL_ID_PIODE);
106 
107 	at91_set_gpio_output(AT91_PIN_PD1, 0);
108 	at91_set_gpio_output(AT91_PIN_PD3, 0);
109 }
110 #endif
111 
112 #ifdef CONFIG_MACB
113 static void picosam9g45_macb_hw_init(void)
114 {
115 	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
116 
117 	at91_periph_clk_enable(ATMEL_ID_EMAC);
118 
119 	/*
120 	 * Disable pull-up on:
121 	 *      RXDV (PA15) => PHY normal mode (not Test mode)
122 	 *      ERX0 (PA12) => PHY ADDR0
123 	 *      ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
124 	 *
125 	 * PHY has internal pull-down
126 	 */
127 	writel(pin_to_mask(AT91_PIN_PA15) |
128 	       pin_to_mask(AT91_PIN_PA12) |
129 	       pin_to_mask(AT91_PIN_PA13),
130 	       &pioa->pudr);
131 
132 	at91_phy_reset();
133 
134 	/* Re-enable pull-up */
135 	writel(pin_to_mask(AT91_PIN_PA15) |
136 	       pin_to_mask(AT91_PIN_PA12) |
137 	       pin_to_mask(AT91_PIN_PA13),
138 	       &pioa->puer);
139 
140 	/* And the pins. */
141 	at91_macb_hw_init();
142 }
143 #endif
144 
145 #ifdef CONFIG_LCD
146 
147 vidinfo_t panel_info = {
148 	.vl_col =		480,
149 	.vl_row =		272,
150 	.vl_clk =		9000000,
151 	.vl_sync =		ATMEL_LCDC_INVLINE_NORMAL |
152 				ATMEL_LCDC_INVFRAME_NORMAL,
153 	.vl_bpix =		3,
154 	.vl_tft =		1,
155 	.vl_hsync_len =		45,
156 	.vl_left_margin =	1,
157 	.vl_right_margin =	1,
158 	.vl_vsync_len =		1,
159 	.vl_upper_margin =	40,
160 	.vl_lower_margin =	1,
161 	.mmio =			ATMEL_BASE_LCDC,
162 };
163 
164 
165 void lcd_enable(void)
166 {
167 	at91_set_A_periph(AT91_PIN_PE6, 1);	/* power up */
168 }
169 
170 void lcd_disable(void)
171 {
172 	at91_set_A_periph(AT91_PIN_PE6, 0);	/* power down */
173 }
174 
175 static void picosam9g45_lcd_hw_init(void)
176 {
177 	at91_set_A_periph(AT91_PIN_PE0, 0);	/* LCDDPWR */
178 	at91_set_A_periph(AT91_PIN_PE2, 0);	/* LCDCC */
179 	at91_set_A_periph(AT91_PIN_PE3, 0);	/* LCDVSYNC */
180 	at91_set_A_periph(AT91_PIN_PE4, 0);	/* LCDHSYNC */
181 	at91_set_A_periph(AT91_PIN_PE5, 0);	/* LCDDOTCK */
182 
183 	at91_set_A_periph(AT91_PIN_PE7, 0);	/* LCDD0 */
184 	at91_set_A_periph(AT91_PIN_PE8, 0);	/* LCDD1 */
185 	at91_set_A_periph(AT91_PIN_PE9, 0);	/* LCDD2 */
186 	at91_set_A_periph(AT91_PIN_PE10, 0);	/* LCDD3 */
187 	at91_set_A_periph(AT91_PIN_PE11, 0);	/* LCDD4 */
188 	at91_set_A_periph(AT91_PIN_PE12, 0);	/* LCDD5 */
189 	at91_set_A_periph(AT91_PIN_PE13, 0);	/* LCDD6 */
190 	at91_set_A_periph(AT91_PIN_PE14, 0);	/* LCDD7 */
191 	at91_set_A_periph(AT91_PIN_PE15, 0);	/* LCDD8 */
192 	at91_set_A_periph(AT91_PIN_PE16, 0);	/* LCDD9 */
193 	at91_set_A_periph(AT91_PIN_PE17, 0);	/* LCDD10 */
194 	at91_set_A_periph(AT91_PIN_PE18, 0);	/* LCDD11 */
195 	at91_set_A_periph(AT91_PIN_PE19, 0);	/* LCDD12 */
196 	at91_set_B_periph(AT91_PIN_PE20, 0);	/* LCDD13 */
197 	at91_set_A_periph(AT91_PIN_PE21, 0);	/* LCDD14 */
198 	at91_set_A_periph(AT91_PIN_PE22, 0);	/* LCDD15 */
199 	at91_set_A_periph(AT91_PIN_PE23, 0);	/* LCDD16 */
200 	at91_set_A_periph(AT91_PIN_PE24, 0);	/* LCDD17 */
201 	at91_set_A_periph(AT91_PIN_PE25, 0);	/* LCDD18 */
202 	at91_set_A_periph(AT91_PIN_PE26, 0);	/* LCDD19 */
203 	at91_set_A_periph(AT91_PIN_PE27, 0);	/* LCDD20 */
204 	at91_set_B_periph(AT91_PIN_PE28, 0);	/* LCDD21 */
205 	at91_set_A_periph(AT91_PIN_PE29, 0);	/* LCDD22 */
206 	at91_set_A_periph(AT91_PIN_PE30, 0);	/* LCDD23 */
207 
208 	at91_periph_clk_enable(ATMEL_ID_LCDC);
209 
210 	gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
211 }
212 
213 #ifdef CONFIG_LCD_INFO
214 #include <nand.h>
215 #include <version.h>
216 
217 void lcd_show_board_info(void)
218 {
219 	ulong dram_size;
220 	int i;
221 	char temp[32];
222 
223 	lcd_printf("%s\n", U_BOOT_VERSION);
224 	lcd_printf("(C) 2015 Inter Act B.V.\n");
225 	lcd_printf("support@interact.nl\n");
226 	lcd_printf("%s CPU at %s MHz\n",
227 		   ATMEL_CPU_NAME,
228 		   strmhz(temp, get_cpu_clk_rate()));
229 
230 	dram_size = 0;
231 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
232 		dram_size += gd->bd->bi_dram[i].size;
233 	lcd_printf("  %ld MB SDRAM\n", dram_size >> 20);
234 }
235 #endif /* CONFIG_LCD_INFO */
236 #endif
237 
238 #ifdef CONFIG_GENERIC_ATMEL_MCI
239 int board_mmc_init(bd_t *bis)
240 {
241 	at91_mci_hw_init();
242 
243 	return atmel_mci_init((void *)ATMEL_BASE_MCI0);
244 }
245 #endif
246 
247 int board_early_init_f(void)
248 {
249 	at91_seriald_hw_init();
250 	return 0;
251 }
252 
253 int board_init(void)
254 {
255 	gd->bd->bi_arch_number = MACH_TYPE_PICOSAM9G45;
256 
257 	/* adress of boot parameters */
258 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
259 
260 #ifdef CONFIG_CMD_USB
261 	picosam9g45_usb_hw_init();
262 #endif
263 #ifdef CONFIG_HAS_DATAFLASH
264 	at91_spi0_hw_init(1 << 0);
265 #endif
266 #ifdef CONFIG_ATMEL_SPI
267 	at91_spi0_hw_init(1 << 4);
268 #endif
269 #ifdef CONFIG_MACB
270 	picosam9g45_macb_hw_init();
271 #endif
272 #ifdef CONFIG_LCD
273 	picosam9g45_lcd_hw_init();
274 #endif
275 	return 0;
276 }
277 
278 int dram_init(void)
279 {
280 	gd->ram_size    = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
281 			+ get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
282 
283 	return 0;
284 }
285 
286 int dram_init_banksize(void)
287 {
288 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
289 	gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
290 							PHYS_SDRAM_1_SIZE);
291 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
292 	gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
293 							PHYS_SDRAM_2_SIZE);
294 
295 	return 0;
296 }
297 
298 #ifdef CONFIG_RESET_PHY_R
299 void reset_phy(void)
300 {
301 }
302 #endif
303 
304 int board_eth_init(bd_t *bis)
305 {
306 	int rc = 0;
307 #ifdef CONFIG_MACB
308 	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
309 #endif
310 	return rc;
311 }
312 
313 /* SPI chip select control */
314 #ifdef CONFIG_ATMEL_SPI
315 #include <spi.h>
316 
317 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
318 {
319 	return bus == 0 && cs < 2;
320 }
321 
322 void spi_cs_activate(struct spi_slave *slave)
323 {
324 	switch (slave->cs) {
325 	case 1:
326 		at91_set_gpio_output(AT91_PIN_PB18, 0);
327 		break;
328 	case 0:
329 	default:
330 		at91_set_gpio_output(AT91_PIN_PB3, 0);
331 		break;
332 	}
333 }
334 
335 void spi_cs_deactivate(struct spi_slave *slave)
336 {
337 	switch (slave->cs) {
338 	case 1:
339 		at91_set_gpio_output(AT91_PIN_PB18, 1);
340 		break;
341 	case 0:
342 	default:
343 		at91_set_gpio_output(AT91_PIN_PB3, 1);
344 	break;
345 	}
346 }
347 #endif /* CONFIG_ATMEL_SPI */
348