1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering 4 * 5 * Copyright (C) 2006 Micronas GmbH 6 */ 7 8 #ifndef _REG_SCC_PREMIUM_H_ 9 #define _REG_SCC_PREMIUM_H_ 10 11 #define SCC0_BASE 0x00110000 12 #define SCC1_BASE 0x00110080 13 #define SCC2_BASE 0x00110100 14 #define SCC3_BASE 0x00110180 15 #define SCC4_BASE 0x00110200 16 #define SCC5_BASE 0x00110280 17 #define SCC6_BASE 0x00110300 18 #define SCC7_BASE 0x00110380 19 #define SCC8_BASE 0x00110400 20 #define SCC9_BASE 0x00110480 21 #define SCC10_BASE 0x00110500 22 #define SCC11_BASE 0x00110580 23 #define SCC12_BASE 0x00110600 24 #define SCC13_BASE 0x00110680 25 #define SCC14_BASE 0x00110700 26 #define SCC15_BASE 0x00110780 27 #define SCC16_BASE 0x00110800 28 #define SCC17_BASE 0x00110880 29 #define SCC18_BASE 0x00110900 30 #define SCC19_BASE 0x00110980 31 #define SCC20_BASE 0x00110a00 32 #define SCC21_BASE 0x00110a80 33 #define SCC22_BASE 0x00110b00 34 #define SCC23_BASE 0x00110b80 35 #define SCC24_BASE 0x00110c00 36 #define SCC25_BASE 0x00110c80 37 #define SCC26_BASE 0x00110d00 38 #define SCC27_BASE 0x00110d80 39 #define SCC28_BASE 0x00110e00 40 #define SCC29_BASE 0x00110e80 41 #define SCC30_BASE 0x00110f00 42 #define SCC31_BASE 0x00110f80 43 #define SCC32_BASE 0x00111000 44 #define SCC33_BASE 0x00111080 45 #define SCC34_BASE 0x00111100 46 #define SCC35_BASE 0x00111180 47 #define SCC36_BASE 0x00111200 48 #define SCC37_BASE 0x00111280 49 #define SCC38_BASE 0x00111300 50 #define SCC39_BASE 0x00111380 51 #define SCC40_BASE 0x00111400 52 53 /* Relative offsets of the register adresses */ 54 55 #define SCC_ENABLE_OFFS 0x00000000 56 #define SCC_ENABLE(base) ((base) + SCC_ENABLE_OFFS) 57 #define SCC_RESET_OFFS 0x00000004 58 #define SCC_RESET(base) ((base) + SCC_RESET_OFFS) 59 #define SCC_VCID_OFFS 0x00000008 60 #define SCC_VCID(base) ((base) + SCC_VCID_OFFS) 61 #define SCC_MCI_CFG_OFFS 0x0000000C 62 #define SCC_MCI_CFG(base) ((base) + SCC_MCI_CFG_OFFS) 63 #define SCC_PACKET_CFG1_OFFS 0x00000010 64 #define SCC_PACKET_CFG1(base) ((base) + SCC_PACKET_CFG1_OFFS) 65 #define SCC_PACKET_CFG2_OFFS 0x00000014 66 #define SCC_PACKET_CFG2(base) ((base) + SCC_PACKET_CFG2_OFFS) 67 #define SCC_PACKET_CFG3_OFFS 0x00000018 68 #define SCC_PACKET_CFG3(base) ((base) + SCC_PACKET_CFG3_OFFS) 69 #define SCC_DMA_CFG_OFFS 0x0000001C 70 #define SCC_DMA_CFG(base) ((base) + SCC_DMA_CFG_OFFS) 71 #define SCC_CMD_OFFS 0x00000020 72 #define SCC_CMD(base) ((base) + SCC_CMD_OFFS) 73 #define SCC_PRIO_OFFS 0x00000024 74 #define SCC_PRIO(base) ((base) + SCC_PRIO_OFFS) 75 #define SCC_DEBUG_OFFS 0x00000028 76 #define SCC_DEBUG(base) ((base) + SCC_DEBUG_OFFS) 77 #define SCC_STATUS_OFFS 0x0000002C 78 #define SCC_STATUS(base) ((base) + SCC_STATUS_OFFS) 79 #define SCC_IMR_OFFS 0x00000030 80 #define SCC_IMR(base) ((base) + SCC_IMR_OFFS) 81 #define SCC_ISR_OFFS 0x00000034 82 #define SCC_ISR(base) ((base) + SCC_ISR_OFFS) 83 #define SCC_DMA_OFFSET_OFFS 0x00000038 84 #define SCC_DMA_OFFSET(base) ((base) + SCC_DMA_OFFSET_OFFS) 85 #define SCC_RS_CTLSTS_OFFS 0x0000003C 86 #define SCC_RS_CTLSTS(base) ((base) + SCC_RS_CTLSTS_OFFS) 87 88 #endif 89