1*2a61eff6SStefan Roese /* 2*2a61eff6SStefan Roese * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering 3*2a61eff6SStefan Roese * 4*2a61eff6SStefan Roese * Copyright (C) 2006 Micronas GmbH 5*2a61eff6SStefan Roese * 6*2a61eff6SStefan Roese * This program is free software; you can redistribute it and/or 7*2a61eff6SStefan Roese * modify it under the terms of the GNU General Public License as 8*2a61eff6SStefan Roese * published by the Free Software Foundation; either version 2 of 9*2a61eff6SStefan Roese * the License, or (at your option) any later version. 10*2a61eff6SStefan Roese * 11*2a61eff6SStefan Roese * This program is distributed in the hope that it will be useful, 12*2a61eff6SStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 13*2a61eff6SStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14*2a61eff6SStefan Roese * GNU General Public License for more details. 15*2a61eff6SStefan Roese * 16*2a61eff6SStefan Roese * You should have received a copy of the GNU General Public License 17*2a61eff6SStefan Roese * along with this program; if not, write to the Free Software 18*2a61eff6SStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19*2a61eff6SStefan Roese * MA 02111-1307 USA 20*2a61eff6SStefan Roese */ 21*2a61eff6SStefan Roese 22*2a61eff6SStefan Roese #ifndef _REG_SCC_PREMIUM_H_ 23*2a61eff6SStefan Roese #define _REG_SCC_PREMIUM_H_ 24*2a61eff6SStefan Roese 25*2a61eff6SStefan Roese #define SCC0_BASE 0x00110000 26*2a61eff6SStefan Roese #define SCC1_BASE 0x00110080 27*2a61eff6SStefan Roese #define SCC2_BASE 0x00110100 28*2a61eff6SStefan Roese #define SCC3_BASE 0x00110180 29*2a61eff6SStefan Roese #define SCC4_BASE 0x00110200 30*2a61eff6SStefan Roese #define SCC5_BASE 0x00110280 31*2a61eff6SStefan Roese #define SCC6_BASE 0x00110300 32*2a61eff6SStefan Roese #define SCC7_BASE 0x00110380 33*2a61eff6SStefan Roese #define SCC8_BASE 0x00110400 34*2a61eff6SStefan Roese #define SCC9_BASE 0x00110480 35*2a61eff6SStefan Roese #define SCC10_BASE 0x00110500 36*2a61eff6SStefan Roese #define SCC11_BASE 0x00110580 37*2a61eff6SStefan Roese #define SCC12_BASE 0x00110600 38*2a61eff6SStefan Roese #define SCC13_BASE 0x00110680 39*2a61eff6SStefan Roese #define SCC14_BASE 0x00110700 40*2a61eff6SStefan Roese #define SCC15_BASE 0x00110780 41*2a61eff6SStefan Roese #define SCC16_BASE 0x00110800 42*2a61eff6SStefan Roese #define SCC17_BASE 0x00110880 43*2a61eff6SStefan Roese #define SCC18_BASE 0x00110900 44*2a61eff6SStefan Roese #define SCC19_BASE 0x00110980 45*2a61eff6SStefan Roese #define SCC20_BASE 0x00110a00 46*2a61eff6SStefan Roese #define SCC21_BASE 0x00110a80 47*2a61eff6SStefan Roese #define SCC22_BASE 0x00110b00 48*2a61eff6SStefan Roese #define SCC23_BASE 0x00110b80 49*2a61eff6SStefan Roese #define SCC24_BASE 0x00110c00 50*2a61eff6SStefan Roese #define SCC25_BASE 0x00110c80 51*2a61eff6SStefan Roese #define SCC26_BASE 0x00110d00 52*2a61eff6SStefan Roese #define SCC27_BASE 0x00110d80 53*2a61eff6SStefan Roese #define SCC28_BASE 0x00110e00 54*2a61eff6SStefan Roese #define SCC29_BASE 0x00110e80 55*2a61eff6SStefan Roese #define SCC30_BASE 0x00110f00 56*2a61eff6SStefan Roese #define SCC31_BASE 0x00110f80 57*2a61eff6SStefan Roese #define SCC32_BASE 0x00111000 58*2a61eff6SStefan Roese #define SCC33_BASE 0x00111080 59*2a61eff6SStefan Roese #define SCC34_BASE 0x00111100 60*2a61eff6SStefan Roese #define SCC35_BASE 0x00111180 61*2a61eff6SStefan Roese #define SCC36_BASE 0x00111200 62*2a61eff6SStefan Roese #define SCC37_BASE 0x00111280 63*2a61eff6SStefan Roese #define SCC38_BASE 0x00111300 64*2a61eff6SStefan Roese #define SCC39_BASE 0x00111380 65*2a61eff6SStefan Roese #define SCC40_BASE 0x00111400 66*2a61eff6SStefan Roese 67*2a61eff6SStefan Roese /* Relative offsets of the register adresses */ 68*2a61eff6SStefan Roese 69*2a61eff6SStefan Roese #define SCC_ENABLE_OFFS 0x00000000 70*2a61eff6SStefan Roese #define SCC_ENABLE(base) ((base) + SCC_ENABLE_OFFS) 71*2a61eff6SStefan Roese #define SCC_RESET_OFFS 0x00000004 72*2a61eff6SStefan Roese #define SCC_RESET(base) ((base) + SCC_RESET_OFFS) 73*2a61eff6SStefan Roese #define SCC_VCID_OFFS 0x00000008 74*2a61eff6SStefan Roese #define SCC_VCID(base) ((base) + SCC_VCID_OFFS) 75*2a61eff6SStefan Roese #define SCC_MCI_CFG_OFFS 0x0000000C 76*2a61eff6SStefan Roese #define SCC_MCI_CFG(base) ((base) + SCC_MCI_CFG_OFFS) 77*2a61eff6SStefan Roese #define SCC_PACKET_CFG1_OFFS 0x00000010 78*2a61eff6SStefan Roese #define SCC_PACKET_CFG1(base) ((base) + SCC_PACKET_CFG1_OFFS) 79*2a61eff6SStefan Roese #define SCC_PACKET_CFG2_OFFS 0x00000014 80*2a61eff6SStefan Roese #define SCC_PACKET_CFG2(base) ((base) + SCC_PACKET_CFG2_OFFS) 81*2a61eff6SStefan Roese #define SCC_PACKET_CFG3_OFFS 0x00000018 82*2a61eff6SStefan Roese #define SCC_PACKET_CFG3(base) ((base) + SCC_PACKET_CFG3_OFFS) 83*2a61eff6SStefan Roese #define SCC_DMA_CFG_OFFS 0x0000001C 84*2a61eff6SStefan Roese #define SCC_DMA_CFG(base) ((base) + SCC_DMA_CFG_OFFS) 85*2a61eff6SStefan Roese #define SCC_CMD_OFFS 0x00000020 86*2a61eff6SStefan Roese #define SCC_CMD(base) ((base) + SCC_CMD_OFFS) 87*2a61eff6SStefan Roese #define SCC_PRIO_OFFS 0x00000024 88*2a61eff6SStefan Roese #define SCC_PRIO(base) ((base) + SCC_PRIO_OFFS) 89*2a61eff6SStefan Roese #define SCC_DEBUG_OFFS 0x00000028 90*2a61eff6SStefan Roese #define SCC_DEBUG(base) ((base) + SCC_DEBUG_OFFS) 91*2a61eff6SStefan Roese #define SCC_STATUS_OFFS 0x0000002C 92*2a61eff6SStefan Roese #define SCC_STATUS(base) ((base) + SCC_STATUS_OFFS) 93*2a61eff6SStefan Roese #define SCC_IMR_OFFS 0x00000030 94*2a61eff6SStefan Roese #define SCC_IMR(base) ((base) + SCC_IMR_OFFS) 95*2a61eff6SStefan Roese #define SCC_ISR_OFFS 0x00000034 96*2a61eff6SStefan Roese #define SCC_ISR(base) ((base) + SCC_ISR_OFFS) 97*2a61eff6SStefan Roese #define SCC_DMA_OFFSET_OFFS 0x00000038 98*2a61eff6SStefan Roese #define SCC_DMA_OFFSET(base) ((base) + SCC_DMA_OFFSET_OFFS) 99*2a61eff6SStefan Roese #define SCC_RS_CTLSTS_OFFS 0x0000003C 100*2a61eff6SStefan Roese #define SCC_RS_CTLSTS(base) ((base) + SCC_RS_CTLSTS_OFFS) 101*2a61eff6SStefan Roese 102*2a61eff6SStefan Roese #endif 103