1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering 4 * 5 * Copyright (C) 2006 Micronas GmbH 6 */ 7 8 #ifndef _REG_EBI_PREMIUM_H_ 9 #define _REG_EBI_PREMIUM_H_ 10 11 #define EBI_BASE 0x00000000 12 13 /* Relative offsets of the register adresses */ 14 15 #define EBI_CPU_IO_ACCS_OFFS 0x00000000 16 #define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) 17 #define EBI_IO_ACCS_DATA_OFFS 0x00000004 18 #define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS) 19 #define EBI_CTRL_OFFS 0x00000008 20 #define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) 21 #define EBI_IRQ_MASK_OFFS 0x00000010 22 #define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) 23 #define EBI_TAG1_SYS_ID_OFFS 0x00000030 24 #define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS) 25 #define EBI_TAG2_SYS_ID_OFFS 0x00000040 26 #define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS) 27 #define EBI_TAG3_SYS_ID_OFFS 0x00000050 28 #define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS) 29 #define EBI_TAG4_SYS_ID_OFFS 0x00000060 30 #define EBI_TAG4_SYS_ID(base) ((base) + EBI_TAG4_SYS_ID_OFFS) 31 #define EBI_GEN_DMA_CTRL_OFFS 0x00000070 32 #define EBI_GEN_DMA_CTRL(base) ((base) + EBI_GEN_DMA_CTRL_OFFS) 33 #define EBI_STATUS_OFFS 0x00000080 34 #define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS) 35 #define EBI_STATUS_DMA_CNT_OFFS 0x00000084 36 #define EBI_STATUS_DMA_CNT(base) ((base) + EBI_STATUS_DMA_CNT_OFFS) 37 #define EBI_SIG_LEVEL_OFFS 0x00000088 38 #define EBI_SIG_LEVEL(base) ((base) + EBI_SIG_LEVEL_OFFS) 39 #define EBI_CTRL_SIG_ACTLV_OFFS 0x0000008C 40 #define EBI_CTRL_SIG_ACTLV(base) ((base) + EBI_CTRL_SIG_ACTLV_OFFS) 41 #define EBI_EXT_ADDR_OFFS 0x000000A0 42 #define EBI_EXT_ADDR(base) ((base) + EBI_EXT_ADDR_OFFS) 43 #define EBI_IRQ_STATUS_OFFS 0x000000B0 44 #define EBI_IRQ_STATUS(base) ((base) + EBI_IRQ_STATUS_OFFS) 45 #define EBI_DEV1_DMA_EXT_ADDR_OFFS 0x00000100 46 #define EBI_DEV1_DMA_EXT_ADDR(base) ((base) + EBI_DEV1_DMA_EXT_ADDR_OFFS) 47 #define EBI_DEV1_EXT_ACC_OFFS 0x00000104 48 #define EBI_DEV1_EXT_ACC(base) ((base) + EBI_DEV1_EXT_ACC_OFFS) 49 #define EBI_DEV1_CONFIG1_OFFS 0x00000108 50 #define EBI_DEV1_CONFIG1(base) ((base) + EBI_DEV1_CONFIG1_OFFS) 51 #define EBI_DEV1_CONFIG2_OFFS 0x0000010C 52 #define EBI_DEV1_CONFIG2(base) ((base) + EBI_DEV1_CONFIG2_OFFS) 53 #define EBI_DEV1_FIFO_CONFIG_OFFS 0x00000110 54 #define EBI_DEV1_FIFO_CONFIG(base) ((base) + EBI_DEV1_FIFO_CONFIG_OFFS) 55 #define EBI_DEV1_FLASH_CONF_ST_OFFS 0x00000114 56 #define EBI_DEV1_FLASH_CONF_ST(base) ((base) + EBI_DEV1_FLASH_CONF_ST_OFFS) 57 #define EBI_DEV1_DMA_CONFIG1_OFFS 0x00000118 58 #define EBI_DEV1_DMA_CONFIG1(base) ((base) + EBI_DEV1_DMA_CONFIG1_OFFS) 59 #define EBI_DEV1_DMA_CONFIG2_OFFS 0x0000011C 60 #define EBI_DEV1_DMA_CONFIG2(base) ((base) + EBI_DEV1_DMA_CONFIG2_OFFS) 61 #define EBI_DEV1_TIM1_RD1_OFFS 0x00000124 62 #define EBI_DEV1_TIM1_RD1(base) ((base) + EBI_DEV1_TIM1_RD1_OFFS) 63 #define EBI_DEV1_TIM1_RD2_OFFS 0x00000128 64 #define EBI_DEV1_TIM1_RD2(base) ((base) + EBI_DEV1_TIM1_RD2_OFFS) 65 #define EBI_DEV1_TIM1_WR1_OFFS 0x0000012C 66 #define EBI_DEV1_TIM1_WR1(base) ((base) + EBI_DEV1_TIM1_WR1_OFFS) 67 #define EBI_DEV1_TIM1_WR2_OFFS 0x00000130 68 #define EBI_DEV1_TIM1_WR2(base) ((base) + EBI_DEV1_TIM1_WR2_OFFS) 69 #define EBI_DEV1_TIM_EXT_OFFS 0x00000134 70 #define EBI_DEV1_TIM_EXT(base) ((base) + EBI_DEV1_TIM_EXT_OFFS) 71 #define EBI_DEV1_TIM2_CFI_RD1_OFFS 0x00000138 72 #define EBI_DEV1_TIM2_CFI_RD1(base) ((base) + EBI_DEV1_TIM2_CFI_RD1_OFFS) 73 #define EBI_DEV1_TIM2_CFI_RD2_OFFS 0x0000013C 74 #define EBI_DEV1_TIM2_CFI_RD2(base) ((base) + EBI_DEV1_TIM2_CFI_RD2_OFFS) 75 #define EBI_DEV1_TIM3_DMA1_OFFS 0x00000140 76 #define EBI_DEV1_TIM3_DMA1(base) ((base) + EBI_DEV1_TIM3_DMA1_OFFS) 77 #define EBI_DEV1_TIM3_DMA2_OFFS 0x00000144 78 #define EBI_DEV1_TIM3_DMA2(base) ((base) + EBI_DEV1_TIM3_DMA2_OFFS) 79 #define EBI_DEV1_ACK_RM_CNT_OFFS 0x00000150 80 #define EBI_DEV1_ACK_RM_CNT(base) ((base) + EBI_DEV1_ACK_RM_CNT_OFFS) 81 #define EBI_DEV2_DMA_EXT_ADDR_OFFS 0x00000200 82 #define EBI_DEV2_DMA_EXT_ADDR(base) ((base) + EBI_DEV2_DMA_EXT_ADDR_OFFS) 83 #define EBI_DEV2_EXT_ACC_OFFS 0x00000204 84 #define EBI_DEV2_EXT_ACC(base) ((base) + EBI_DEV2_EXT_ACC_OFFS) 85 #define EBI_DEV2_CONFIG1_OFFS 0x00000208 86 #define EBI_DEV2_CONFIG1(base) ((base) + EBI_DEV2_CONFIG1_OFFS) 87 #define EBI_DEV2_CONFIG2_OFFS 0x0000020C 88 #define EBI_DEV2_CONFIG2(base) ((base) + EBI_DEV2_CONFIG2_OFFS) 89 #define EBI_DEV2_FIFO_CONFIG_OFFS 0x00000210 90 #define EBI_DEV2_FIFO_CONFIG(base) ((base) + EBI_DEV2_FIFO_CONFIG_OFFS) 91 #define EBI_DEV2_FLASH_CONF_ST_OFFS 0x00000214 92 #define EBI_DEV2_FLASH_CONF_ST(base) ((base) + EBI_DEV2_FLASH_CONF_ST_OFFS) 93 #define EBI_DEV2_DMA_CONFIG1_OFFS 0x00000218 94 #define EBI_DEV2_DMA_CONFIG1(base) ((base) + EBI_DEV2_DMA_CONFIG1_OFFS) 95 #define EBI_DEV2_DMA_CONFIG2_OFFS 0x0000021C 96 #define EBI_DEV2_DMA_CONFIG2(base) ((base) + EBI_DEV2_DMA_CONFIG2_OFFS) 97 #define EBI_DEV2_TIM1_RD1_OFFS 0x00000224 98 #define EBI_DEV2_TIM1_RD1(base) ((base) + EBI_DEV2_TIM1_RD1_OFFS) 99 #define EBI_DEV2_TIM1_RD2_OFFS 0x00000228 100 #define EBI_DEV2_TIM1_RD2(base) ((base) + EBI_DEV2_TIM1_RD2_OFFS) 101 #define EBI_DEV2_TIM1_WR1_OFFS 0x0000022C 102 #define EBI_DEV2_TIM1_WR1(base) ((base) + EBI_DEV2_TIM1_WR1_OFFS) 103 #define EBI_DEV2_TIM1_WR2_OFFS 0x00000230 104 #define EBI_DEV2_TIM1_WR2(base) ((base) + EBI_DEV2_TIM1_WR2_OFFS) 105 #define EBI_DEV2_TIM_EXT_OFFS 0x00000234 106 #define EBI_DEV2_TIM_EXT(base) ((base) + EBI_DEV2_TIM_EXT_OFFS) 107 #define EBI_DEV2_TIM2_CFI_RD1_OFFS 0x00000238 108 #define EBI_DEV2_TIM2_CFI_RD1(base) ((base) + EBI_DEV2_TIM2_CFI_RD1_OFFS) 109 #define EBI_DEV2_TIM2_CFI_RD2_OFFS 0x0000023C 110 #define EBI_DEV2_TIM2_CFI_RD2(base) ((base) + EBI_DEV2_TIM2_CFI_RD2_OFFS) 111 #define EBI_DEV2_TIM3_DMA1_OFFS 0x00000240 112 #define EBI_DEV2_TIM3_DMA1(base) ((base) + EBI_DEV2_TIM3_DMA1_OFFS) 113 #define EBI_DEV2_TIM3_DMA2_OFFS 0x00000244 114 #define EBI_DEV2_TIM3_DMA2(base) ((base) + EBI_DEV2_TIM3_DMA2_OFFS) 115 #define EBI_DEV2_ACK_RM_CNT_OFFS 0x00000250 116 #define EBI_DEV2_ACK_RM_CNT(base) ((base) + EBI_DEV2_ACK_RM_CNT_OFFS) 117 #define EBI_DEV3_DMA_EXT_ADDR_OFFS 0x00000300 118 #define EBI_DEV3_DMA_EXT_ADDR(base) ((base) + EBI_DEV3_DMA_EXT_ADDR_OFFS) 119 #define EBI_DEV3_EXT_ACC_OFFS 0x00000304 120 #define EBI_DEV3_EXT_ACC(base) ((base) + EBI_DEV3_EXT_ACC_OFFS) 121 #define EBI_DEV3_CONFIG1_OFFS 0x00000308 122 #define EBI_DEV3_CONFIG1(base) ((base) + EBI_DEV3_CONFIG1_OFFS) 123 #define EBI_DEV3_CONFIG2_OFFS 0x0000030C 124 #define EBI_DEV3_CONFIG2(base) ((base) + EBI_DEV3_CONFIG2_OFFS) 125 #define EBI_DEV3_FIFO_CONFIG_OFFS 0x00000310 126 #define EBI_DEV3_FIFO_CONFIG(base) ((base) + EBI_DEV3_FIFO_CONFIG_OFFS) 127 #define EBI_DEV3_FLASH_CONF_ST_OFFS 0x00000314 128 #define EBI_DEV3_FLASH_CONF_ST(base) ((base) + EBI_DEV3_FLASH_CONF_ST_OFFS) 129 #define EBI_DEV3_DMA_CONFIG1_OFFS 0x00000318 130 #define EBI_DEV3_DMA_CONFIG1(base) ((base) + EBI_DEV3_DMA_CONFIG1_OFFS) 131 #define EBI_DEV3_DMA_CONFIG2_OFFS 0x0000031C 132 #define EBI_DEV3_DMA_CONFIG2(base) ((base) + EBI_DEV3_DMA_CONFIG2_OFFS) 133 #define EBI_DEV3_TIM1_RD1_OFFS 0x00000324 134 #define EBI_DEV3_TIM1_RD1(base) ((base) + EBI_DEV3_TIM1_RD1_OFFS) 135 #define EBI_DEV3_TIM1_RD2_OFFS 0x00000328 136 #define EBI_DEV3_TIM1_RD2(base) ((base) + EBI_DEV3_TIM1_RD2_OFFS) 137 #define EBI_DEV3_TIM1_WR1_OFFS 0x0000032C 138 #define EBI_DEV3_TIM1_WR1(base) ((base) + EBI_DEV3_TIM1_WR1_OFFS) 139 #define EBI_DEV3_TIM1_WR2_OFFS 0x00000330 140 #define EBI_DEV3_TIM1_WR2(base) ((base) + EBI_DEV3_TIM1_WR2_OFFS) 141 #define EBI_DEV3_TIM_EXT_OFFS 0x00000334 142 #define EBI_DEV3_TIM_EXT(base) ((base) + EBI_DEV3_TIM_EXT_OFFS) 143 #define EBI_DEV3_TIM2_CFI_RD1_OFFS 0x00000338 144 #define EBI_DEV3_TIM2_CFI_RD1(base) ((base) + EBI_DEV3_TIM2_CFI_RD1_OFFS) 145 #define EBI_DEV3_TIM2_CFI_RD2_OFFS 0x0000033C 146 #define EBI_DEV3_TIM2_CFI_RD2(base) ((base) + EBI_DEV3_TIM2_CFI_RD2_OFFS) 147 #define EBI_DEV3_TIM3_DMA1_OFFS 0x00000340 148 #define EBI_DEV3_TIM3_DMA1(base) ((base) + EBI_DEV3_TIM3_DMA1_OFFS) 149 #define EBI_DEV3_TIM3_DMA2_OFFS 0x00000344 150 #define EBI_DEV3_TIM3_DMA2(base) ((base) + EBI_DEV3_TIM3_DMA2_OFFS) 151 #define EBI_DEV3_ACK_RM_CNT_OFFS 0x00000350 152 #define EBI_DEV3_ACK_RM_CNT(base) ((base) + EBI_DEV3_ACK_RM_CNT_OFFS) 153 #define EBI_DEV4_DMA_EXT_ADDR_OFFS 0x00000400 154 #define EBI_DEV4_DMA_EXT_ADDR(base) ((base) + EBI_DEV4_DMA_EXT_ADDR_OFFS) 155 #define EBI_DEV4_EXT_ACC_OFFS 0x00000404 156 #define EBI_DEV4_EXT_ACC(base) ((base) + EBI_DEV4_EXT_ACC_OFFS) 157 #define EBI_DEV4_CONFIG1_OFFS 0x00000408 158 #define EBI_DEV4_CONFIG1(base) ((base) + EBI_DEV4_CONFIG1_OFFS) 159 #define EBI_DEV4_CONFIG2_OFFS 0x0000040C 160 #define EBI_DEV4_CONFIG2(base) ((base) + EBI_DEV4_CONFIG2_OFFS) 161 #define EBI_DEV4_FIFO_CONFIG_OFFS 0x00000410 162 #define EBI_DEV4_FIFO_CONFIG(base) ((base) + EBI_DEV4_FIFO_CONFIG_OFFS) 163 #define EBI_DEV4_FLASH_CONF_ST_OFFS 0x00000414 164 #define EBI_DEV4_FLASH_CONF_ST(base) ((base) + EBI_DEV4_FLASH_CONF_ST_OFFS) 165 #define EBI_DEV4_DMA_CONFIG1_OFFS 0x00000418 166 #define EBI_DEV4_DMA_CONFIG1(base) ((base) + EBI_DEV4_DMA_CONFIG1_OFFS) 167 #define EBI_DEV4_DMA_CONFIG2_OFFS 0x0000041C 168 #define EBI_DEV4_DMA_CONFIG2(base) ((base) + EBI_DEV4_DMA_CONFIG2_OFFS) 169 #define EBI_DEV4_TIM1_RD1_OFFS 0x00000424 170 #define EBI_DEV4_TIM1_RD1(base) ((base) + EBI_DEV4_TIM1_RD1_OFFS) 171 #define EBI_DEV4_TIM1_RD2_OFFS 0x00000428 172 #define EBI_DEV4_TIM1_RD2(base) ((base) + EBI_DEV4_TIM1_RD2_OFFS) 173 #define EBI_DEV4_TIM1_WR1_OFFS 0x0000042C 174 #define EBI_DEV4_TIM1_WR1(base) ((base) + EBI_DEV4_TIM1_WR1_OFFS) 175 #define EBI_DEV4_TIM1_WR2_OFFS 0x00000430 176 #define EBI_DEV4_TIM1_WR2(base) ((base) + EBI_DEV4_TIM1_WR2_OFFS) 177 #define EBI_DEV4_TIM_EXT_OFFS 0x00000434 178 #define EBI_DEV4_TIM_EXT(base) ((base) + EBI_DEV4_TIM_EXT_OFFS) 179 #define EBI_DEV4_TIM2_CFI_RD1_OFFS 0x00000438 180 #define EBI_DEV4_TIM2_CFI_RD1(base) ((base) + EBI_DEV4_TIM2_CFI_RD1_OFFS) 181 #define EBI_DEV4_TIM2_CFI_RD2_OFFS 0x0000043C 182 #define EBI_DEV4_TIM2_CFI_RD2(base) ((base) + EBI_DEV4_TIM2_CFI_RD2_OFFS) 183 #define EBI_DEV4_TIM3_DMA1_OFFS 0x00000440 184 #define EBI_DEV4_TIM3_DMA1(base) ((base) + EBI_DEV4_TIM3_DMA1_OFFS) 185 #define EBI_DEV4_TIM3_DMA2_OFFS 0x00000444 186 #define EBI_DEV4_TIM3_DMA2(base) ((base) + EBI_DEV4_TIM3_DMA2_OFFS) 187 #define EBI_DEV4_ACK_RM_CNT_OFFS 0x00000450 188 #define EBI_DEV4_ACK_RM_CNT(base) ((base) + EBI_DEV4_ACK_RM_CNT_OFFS) 189 #define EBI_CNT_FL_PROGR_OFFS 0x00000904 190 #define EBI_CNT_FL_PROGR(base) ((base) + EBI_CNT_FL_PROGR_OFFS) 191 #define EBI_CNT_EXT_PAGE_SZ_OFFS 0x0000090C 192 #define EBI_CNT_EXT_PAGE_SZ(base) ((base) + EBI_CNT_EXT_PAGE_SZ_OFFS) 193 #define EBI_CNT_WAIT_RDY_OFFS 0x00000914 194 #define EBI_CNT_WAIT_RDY(base) ((base) + EBI_CNT_WAIT_RDY_OFFS) 195 #define EBI_CNT_ACK_OFFS 0x00000918 196 #define EBI_CNT_ACK(base) ((base) + EBI_CNT_ACK_OFFS) 197 #define EBI_GENIO1_CONFIG1_OFFS 0x00000A00 198 #define EBI_GENIO1_CONFIG1(base) ((base) + EBI_GENIO1_CONFIG1_OFFS) 199 #define EBI_GENIO1_CONFIG2_OFFS 0x00000A04 200 #define EBI_GENIO1_CONFIG2(base) ((base) + EBI_GENIO1_CONFIG2_OFFS) 201 #define EBI_GENIO1_CONFIG3_OFFS 0x00000A08 202 #define EBI_GENIO1_CONFIG3(base) ((base) + EBI_GENIO1_CONFIG3_OFFS) 203 #define EBI_GENIO2_CONFIG1_OFFS 0x00000A10 204 #define EBI_GENIO2_CONFIG1(base) ((base) + EBI_GENIO2_CONFIG1_OFFS) 205 #define EBI_GENIO2_CONFIG2_OFFS 0x00000A14 206 #define EBI_GENIO2_CONFIG2(base) ((base) + EBI_GENIO2_CONFIG2_OFFS) 207 #define EBI_GENIO2_CONFIG3_OFFS 0x00000A18 208 #define EBI_GENIO2_CONFIG3(base) ((base) + EBI_GENIO2_CONFIG3_OFFS) 209 #define EBI_GENIO3_CONFIG1_OFFS 0x00000A20 210 #define EBI_GENIO3_CONFIG1(base) ((base) + EBI_GENIO3_CONFIG1_OFFS) 211 #define EBI_GENIO3_CONFIG2_OFFS 0x00000A24 212 #define EBI_GENIO3_CONFIG2(base) ((base) + EBI_GENIO3_CONFIG2_OFFS) 213 #define EBI_GENIO3_CONFIG3_OFFS 0x00000A28 214 #define EBI_GENIO3_CONFIG3(base) ((base) + EBI_GENIO3_CONFIG3_OFFS) 215 #define EBI_GENIO4_CONFIG1_OFFS 0x00000A30 216 #define EBI_GENIO4_CONFIG1(base) ((base) + EBI_GENIO4_CONFIG1_OFFS) 217 #define EBI_GENIO4_CONFIG2_OFFS 0x00000A34 218 #define EBI_GENIO4_CONFIG2(base) ((base) + EBI_GENIO4_CONFIG2_OFFS) 219 #define EBI_GENIO4_CONFIG3_OFFS 0x00000A38 220 #define EBI_GENIO4_CONFIG3(base) ((base) + EBI_GENIO4_CONFIG3_OFFS) 221 #define EBI_GENIO5_CONFIG1_OFFS 0x00000A40 222 #define EBI_GENIO5_CONFIG1(base) ((base) + EBI_GENIO5_CONFIG1_OFFS) 223 #define EBI_GENIO5_CONFIG2_OFFS 0x00000A44 224 #define EBI_GENIO5_CONFIG2(base) ((base) + EBI_GENIO5_CONFIG2_OFFS) 225 #define EBI_GENIO5_CONFIG3_OFFS 0x00000A48 226 #define EBI_GENIO5_CONFIG3(base) ((base) + EBI_GENIO5_CONFIG3_OFFS) 227 228 #endif 229