1 /* 2 * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering 3 * 4 * Copyright (C) 2006 Micronas GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 */ 21 22 #ifndef _REG_EBI_PREMIUM_H_ 23 #define _REG_EBI_PREMIUM_H_ 24 25 #define EBI_BASE 0x00000000 26 27 /* Relative offsets of the register adresses */ 28 29 #define EBI_CPU_IO_ACCS_OFFS 0x00000000 30 #define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) 31 #define EBI_IO_ACCS_DATA_OFFS 0x00000004 32 #define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS) 33 #define EBI_CTRL_OFFS 0x00000008 34 #define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) 35 #define EBI_IRQ_MASK_OFFS 0x00000010 36 #define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) 37 #define EBI_TAG1_SYS_ID_OFFS 0x00000030 38 #define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS) 39 #define EBI_TAG2_SYS_ID_OFFS 0x00000040 40 #define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS) 41 #define EBI_TAG3_SYS_ID_OFFS 0x00000050 42 #define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS) 43 #define EBI_TAG4_SYS_ID_OFFS 0x00000060 44 #define EBI_TAG4_SYS_ID(base) ((base) + EBI_TAG4_SYS_ID_OFFS) 45 #define EBI_GEN_DMA_CTRL_OFFS 0x00000070 46 #define EBI_GEN_DMA_CTRL(base) ((base) + EBI_GEN_DMA_CTRL_OFFS) 47 #define EBI_STATUS_OFFS 0x00000080 48 #define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS) 49 #define EBI_STATUS_DMA_CNT_OFFS 0x00000084 50 #define EBI_STATUS_DMA_CNT(base) ((base) + EBI_STATUS_DMA_CNT_OFFS) 51 #define EBI_SIG_LEVEL_OFFS 0x00000088 52 #define EBI_SIG_LEVEL(base) ((base) + EBI_SIG_LEVEL_OFFS) 53 #define EBI_CTRL_SIG_ACTLV_OFFS 0x0000008C 54 #define EBI_CTRL_SIG_ACTLV(base) ((base) + EBI_CTRL_SIG_ACTLV_OFFS) 55 #define EBI_EXT_ADDR_OFFS 0x000000A0 56 #define EBI_EXT_ADDR(base) ((base) + EBI_EXT_ADDR_OFFS) 57 #define EBI_IRQ_STATUS_OFFS 0x000000B0 58 #define EBI_IRQ_STATUS(base) ((base) + EBI_IRQ_STATUS_OFFS) 59 #define EBI_DEV1_DMA_EXT_ADDR_OFFS 0x00000100 60 #define EBI_DEV1_DMA_EXT_ADDR(base) ((base) + EBI_DEV1_DMA_EXT_ADDR_OFFS) 61 #define EBI_DEV1_EXT_ACC_OFFS 0x00000104 62 #define EBI_DEV1_EXT_ACC(base) ((base) + EBI_DEV1_EXT_ACC_OFFS) 63 #define EBI_DEV1_CONFIG1_OFFS 0x00000108 64 #define EBI_DEV1_CONFIG1(base) ((base) + EBI_DEV1_CONFIG1_OFFS) 65 #define EBI_DEV1_CONFIG2_OFFS 0x0000010C 66 #define EBI_DEV1_CONFIG2(base) ((base) + EBI_DEV1_CONFIG2_OFFS) 67 #define EBI_DEV1_FIFO_CONFIG_OFFS 0x00000110 68 #define EBI_DEV1_FIFO_CONFIG(base) ((base) + EBI_DEV1_FIFO_CONFIG_OFFS) 69 #define EBI_DEV1_FLASH_CONF_ST_OFFS 0x00000114 70 #define EBI_DEV1_FLASH_CONF_ST(base) ((base) + EBI_DEV1_FLASH_CONF_ST_OFFS) 71 #define EBI_DEV1_DMA_CONFIG1_OFFS 0x00000118 72 #define EBI_DEV1_DMA_CONFIG1(base) ((base) + EBI_DEV1_DMA_CONFIG1_OFFS) 73 #define EBI_DEV1_DMA_CONFIG2_OFFS 0x0000011C 74 #define EBI_DEV1_DMA_CONFIG2(base) ((base) + EBI_DEV1_DMA_CONFIG2_OFFS) 75 #define EBI_DEV1_TIM1_RD1_OFFS 0x00000124 76 #define EBI_DEV1_TIM1_RD1(base) ((base) + EBI_DEV1_TIM1_RD1_OFFS) 77 #define EBI_DEV1_TIM1_RD2_OFFS 0x00000128 78 #define EBI_DEV1_TIM1_RD2(base) ((base) + EBI_DEV1_TIM1_RD2_OFFS) 79 #define EBI_DEV1_TIM1_WR1_OFFS 0x0000012C 80 #define EBI_DEV1_TIM1_WR1(base) ((base) + EBI_DEV1_TIM1_WR1_OFFS) 81 #define EBI_DEV1_TIM1_WR2_OFFS 0x00000130 82 #define EBI_DEV1_TIM1_WR2(base) ((base) + EBI_DEV1_TIM1_WR2_OFFS) 83 #define EBI_DEV1_TIM_EXT_OFFS 0x00000134 84 #define EBI_DEV1_TIM_EXT(base) ((base) + EBI_DEV1_TIM_EXT_OFFS) 85 #define EBI_DEV1_TIM2_CFI_RD1_OFFS 0x00000138 86 #define EBI_DEV1_TIM2_CFI_RD1(base) ((base) + EBI_DEV1_TIM2_CFI_RD1_OFFS) 87 #define EBI_DEV1_TIM2_CFI_RD2_OFFS 0x0000013C 88 #define EBI_DEV1_TIM2_CFI_RD2(base) ((base) + EBI_DEV1_TIM2_CFI_RD2_OFFS) 89 #define EBI_DEV1_TIM3_DMA1_OFFS 0x00000140 90 #define EBI_DEV1_TIM3_DMA1(base) ((base) + EBI_DEV1_TIM3_DMA1_OFFS) 91 #define EBI_DEV1_TIM3_DMA2_OFFS 0x00000144 92 #define EBI_DEV1_TIM3_DMA2(base) ((base) + EBI_DEV1_TIM3_DMA2_OFFS) 93 #define EBI_DEV1_ACK_RM_CNT_OFFS 0x00000150 94 #define EBI_DEV1_ACK_RM_CNT(base) ((base) + EBI_DEV1_ACK_RM_CNT_OFFS) 95 #define EBI_DEV2_DMA_EXT_ADDR_OFFS 0x00000200 96 #define EBI_DEV2_DMA_EXT_ADDR(base) ((base) + EBI_DEV2_DMA_EXT_ADDR_OFFS) 97 #define EBI_DEV2_EXT_ACC_OFFS 0x00000204 98 #define EBI_DEV2_EXT_ACC(base) ((base) + EBI_DEV2_EXT_ACC_OFFS) 99 #define EBI_DEV2_CONFIG1_OFFS 0x00000208 100 #define EBI_DEV2_CONFIG1(base) ((base) + EBI_DEV2_CONFIG1_OFFS) 101 #define EBI_DEV2_CONFIG2_OFFS 0x0000020C 102 #define EBI_DEV2_CONFIG2(base) ((base) + EBI_DEV2_CONFIG2_OFFS) 103 #define EBI_DEV2_FIFO_CONFIG_OFFS 0x00000210 104 #define EBI_DEV2_FIFO_CONFIG(base) ((base) + EBI_DEV2_FIFO_CONFIG_OFFS) 105 #define EBI_DEV2_FLASH_CONF_ST_OFFS 0x00000214 106 #define EBI_DEV2_FLASH_CONF_ST(base) ((base) + EBI_DEV2_FLASH_CONF_ST_OFFS) 107 #define EBI_DEV2_DMA_CONFIG1_OFFS 0x00000218 108 #define EBI_DEV2_DMA_CONFIG1(base) ((base) + EBI_DEV2_DMA_CONFIG1_OFFS) 109 #define EBI_DEV2_DMA_CONFIG2_OFFS 0x0000021C 110 #define EBI_DEV2_DMA_CONFIG2(base) ((base) + EBI_DEV2_DMA_CONFIG2_OFFS) 111 #define EBI_DEV2_TIM1_RD1_OFFS 0x00000224 112 #define EBI_DEV2_TIM1_RD1(base) ((base) + EBI_DEV2_TIM1_RD1_OFFS) 113 #define EBI_DEV2_TIM1_RD2_OFFS 0x00000228 114 #define EBI_DEV2_TIM1_RD2(base) ((base) + EBI_DEV2_TIM1_RD2_OFFS) 115 #define EBI_DEV2_TIM1_WR1_OFFS 0x0000022C 116 #define EBI_DEV2_TIM1_WR1(base) ((base) + EBI_DEV2_TIM1_WR1_OFFS) 117 #define EBI_DEV2_TIM1_WR2_OFFS 0x00000230 118 #define EBI_DEV2_TIM1_WR2(base) ((base) + EBI_DEV2_TIM1_WR2_OFFS) 119 #define EBI_DEV2_TIM_EXT_OFFS 0x00000234 120 #define EBI_DEV2_TIM_EXT(base) ((base) + EBI_DEV2_TIM_EXT_OFFS) 121 #define EBI_DEV2_TIM2_CFI_RD1_OFFS 0x00000238 122 #define EBI_DEV2_TIM2_CFI_RD1(base) ((base) + EBI_DEV2_TIM2_CFI_RD1_OFFS) 123 #define EBI_DEV2_TIM2_CFI_RD2_OFFS 0x0000023C 124 #define EBI_DEV2_TIM2_CFI_RD2(base) ((base) + EBI_DEV2_TIM2_CFI_RD2_OFFS) 125 #define EBI_DEV2_TIM3_DMA1_OFFS 0x00000240 126 #define EBI_DEV2_TIM3_DMA1(base) ((base) + EBI_DEV2_TIM3_DMA1_OFFS) 127 #define EBI_DEV2_TIM3_DMA2_OFFS 0x00000244 128 #define EBI_DEV2_TIM3_DMA2(base) ((base) + EBI_DEV2_TIM3_DMA2_OFFS) 129 #define EBI_DEV2_ACK_RM_CNT_OFFS 0x00000250 130 #define EBI_DEV2_ACK_RM_CNT(base) ((base) + EBI_DEV2_ACK_RM_CNT_OFFS) 131 #define EBI_DEV3_DMA_EXT_ADDR_OFFS 0x00000300 132 #define EBI_DEV3_DMA_EXT_ADDR(base) ((base) + EBI_DEV3_DMA_EXT_ADDR_OFFS) 133 #define EBI_DEV3_EXT_ACC_OFFS 0x00000304 134 #define EBI_DEV3_EXT_ACC(base) ((base) + EBI_DEV3_EXT_ACC_OFFS) 135 #define EBI_DEV3_CONFIG1_OFFS 0x00000308 136 #define EBI_DEV3_CONFIG1(base) ((base) + EBI_DEV3_CONFIG1_OFFS) 137 #define EBI_DEV3_CONFIG2_OFFS 0x0000030C 138 #define EBI_DEV3_CONFIG2(base) ((base) + EBI_DEV3_CONFIG2_OFFS) 139 #define EBI_DEV3_FIFO_CONFIG_OFFS 0x00000310 140 #define EBI_DEV3_FIFO_CONFIG(base) ((base) + EBI_DEV3_FIFO_CONFIG_OFFS) 141 #define EBI_DEV3_FLASH_CONF_ST_OFFS 0x00000314 142 #define EBI_DEV3_FLASH_CONF_ST(base) ((base) + EBI_DEV3_FLASH_CONF_ST_OFFS) 143 #define EBI_DEV3_DMA_CONFIG1_OFFS 0x00000318 144 #define EBI_DEV3_DMA_CONFIG1(base) ((base) + EBI_DEV3_DMA_CONFIG1_OFFS) 145 #define EBI_DEV3_DMA_CONFIG2_OFFS 0x0000031C 146 #define EBI_DEV3_DMA_CONFIG2(base) ((base) + EBI_DEV3_DMA_CONFIG2_OFFS) 147 #define EBI_DEV3_TIM1_RD1_OFFS 0x00000324 148 #define EBI_DEV3_TIM1_RD1(base) ((base) + EBI_DEV3_TIM1_RD1_OFFS) 149 #define EBI_DEV3_TIM1_RD2_OFFS 0x00000328 150 #define EBI_DEV3_TIM1_RD2(base) ((base) + EBI_DEV3_TIM1_RD2_OFFS) 151 #define EBI_DEV3_TIM1_WR1_OFFS 0x0000032C 152 #define EBI_DEV3_TIM1_WR1(base) ((base) + EBI_DEV3_TIM1_WR1_OFFS) 153 #define EBI_DEV3_TIM1_WR2_OFFS 0x00000330 154 #define EBI_DEV3_TIM1_WR2(base) ((base) + EBI_DEV3_TIM1_WR2_OFFS) 155 #define EBI_DEV3_TIM_EXT_OFFS 0x00000334 156 #define EBI_DEV3_TIM_EXT(base) ((base) + EBI_DEV3_TIM_EXT_OFFS) 157 #define EBI_DEV3_TIM2_CFI_RD1_OFFS 0x00000338 158 #define EBI_DEV3_TIM2_CFI_RD1(base) ((base) + EBI_DEV3_TIM2_CFI_RD1_OFFS) 159 #define EBI_DEV3_TIM2_CFI_RD2_OFFS 0x0000033C 160 #define EBI_DEV3_TIM2_CFI_RD2(base) ((base) + EBI_DEV3_TIM2_CFI_RD2_OFFS) 161 #define EBI_DEV3_TIM3_DMA1_OFFS 0x00000340 162 #define EBI_DEV3_TIM3_DMA1(base) ((base) + EBI_DEV3_TIM3_DMA1_OFFS) 163 #define EBI_DEV3_TIM3_DMA2_OFFS 0x00000344 164 #define EBI_DEV3_TIM3_DMA2(base) ((base) + EBI_DEV3_TIM3_DMA2_OFFS) 165 #define EBI_DEV3_ACK_RM_CNT_OFFS 0x00000350 166 #define EBI_DEV3_ACK_RM_CNT(base) ((base) + EBI_DEV3_ACK_RM_CNT_OFFS) 167 #define EBI_DEV4_DMA_EXT_ADDR_OFFS 0x00000400 168 #define EBI_DEV4_DMA_EXT_ADDR(base) ((base) + EBI_DEV4_DMA_EXT_ADDR_OFFS) 169 #define EBI_DEV4_EXT_ACC_OFFS 0x00000404 170 #define EBI_DEV4_EXT_ACC(base) ((base) + EBI_DEV4_EXT_ACC_OFFS) 171 #define EBI_DEV4_CONFIG1_OFFS 0x00000408 172 #define EBI_DEV4_CONFIG1(base) ((base) + EBI_DEV4_CONFIG1_OFFS) 173 #define EBI_DEV4_CONFIG2_OFFS 0x0000040C 174 #define EBI_DEV4_CONFIG2(base) ((base) + EBI_DEV4_CONFIG2_OFFS) 175 #define EBI_DEV4_FIFO_CONFIG_OFFS 0x00000410 176 #define EBI_DEV4_FIFO_CONFIG(base) ((base) + EBI_DEV4_FIFO_CONFIG_OFFS) 177 #define EBI_DEV4_FLASH_CONF_ST_OFFS 0x00000414 178 #define EBI_DEV4_FLASH_CONF_ST(base) ((base) + EBI_DEV4_FLASH_CONF_ST_OFFS) 179 #define EBI_DEV4_DMA_CONFIG1_OFFS 0x00000418 180 #define EBI_DEV4_DMA_CONFIG1(base) ((base) + EBI_DEV4_DMA_CONFIG1_OFFS) 181 #define EBI_DEV4_DMA_CONFIG2_OFFS 0x0000041C 182 #define EBI_DEV4_DMA_CONFIG2(base) ((base) + EBI_DEV4_DMA_CONFIG2_OFFS) 183 #define EBI_DEV4_TIM1_RD1_OFFS 0x00000424 184 #define EBI_DEV4_TIM1_RD1(base) ((base) + EBI_DEV4_TIM1_RD1_OFFS) 185 #define EBI_DEV4_TIM1_RD2_OFFS 0x00000428 186 #define EBI_DEV4_TIM1_RD2(base) ((base) + EBI_DEV4_TIM1_RD2_OFFS) 187 #define EBI_DEV4_TIM1_WR1_OFFS 0x0000042C 188 #define EBI_DEV4_TIM1_WR1(base) ((base) + EBI_DEV4_TIM1_WR1_OFFS) 189 #define EBI_DEV4_TIM1_WR2_OFFS 0x00000430 190 #define EBI_DEV4_TIM1_WR2(base) ((base) + EBI_DEV4_TIM1_WR2_OFFS) 191 #define EBI_DEV4_TIM_EXT_OFFS 0x00000434 192 #define EBI_DEV4_TIM_EXT(base) ((base) + EBI_DEV4_TIM_EXT_OFFS) 193 #define EBI_DEV4_TIM2_CFI_RD1_OFFS 0x00000438 194 #define EBI_DEV4_TIM2_CFI_RD1(base) ((base) + EBI_DEV4_TIM2_CFI_RD1_OFFS) 195 #define EBI_DEV4_TIM2_CFI_RD2_OFFS 0x0000043C 196 #define EBI_DEV4_TIM2_CFI_RD2(base) ((base) + EBI_DEV4_TIM2_CFI_RD2_OFFS) 197 #define EBI_DEV4_TIM3_DMA1_OFFS 0x00000440 198 #define EBI_DEV4_TIM3_DMA1(base) ((base) + EBI_DEV4_TIM3_DMA1_OFFS) 199 #define EBI_DEV4_TIM3_DMA2_OFFS 0x00000444 200 #define EBI_DEV4_TIM3_DMA2(base) ((base) + EBI_DEV4_TIM3_DMA2_OFFS) 201 #define EBI_DEV4_ACK_RM_CNT_OFFS 0x00000450 202 #define EBI_DEV4_ACK_RM_CNT(base) ((base) + EBI_DEV4_ACK_RM_CNT_OFFS) 203 #define EBI_CNT_FL_PROGR_OFFS 0x00000904 204 #define EBI_CNT_FL_PROGR(base) ((base) + EBI_CNT_FL_PROGR_OFFS) 205 #define EBI_CNT_EXT_PAGE_SZ_OFFS 0x0000090C 206 #define EBI_CNT_EXT_PAGE_SZ(base) ((base) + EBI_CNT_EXT_PAGE_SZ_OFFS) 207 #define EBI_CNT_WAIT_RDY_OFFS 0x00000914 208 #define EBI_CNT_WAIT_RDY(base) ((base) + EBI_CNT_WAIT_RDY_OFFS) 209 #define EBI_CNT_ACK_OFFS 0x00000918 210 #define EBI_CNT_ACK(base) ((base) + EBI_CNT_ACK_OFFS) 211 #define EBI_GENIO1_CONFIG1_OFFS 0x00000A00 212 #define EBI_GENIO1_CONFIG1(base) ((base) + EBI_GENIO1_CONFIG1_OFFS) 213 #define EBI_GENIO1_CONFIG2_OFFS 0x00000A04 214 #define EBI_GENIO1_CONFIG2(base) ((base) + EBI_GENIO1_CONFIG2_OFFS) 215 #define EBI_GENIO1_CONFIG3_OFFS 0x00000A08 216 #define EBI_GENIO1_CONFIG3(base) ((base) + EBI_GENIO1_CONFIG3_OFFS) 217 #define EBI_GENIO2_CONFIG1_OFFS 0x00000A10 218 #define EBI_GENIO2_CONFIG1(base) ((base) + EBI_GENIO2_CONFIG1_OFFS) 219 #define EBI_GENIO2_CONFIG2_OFFS 0x00000A14 220 #define EBI_GENIO2_CONFIG2(base) ((base) + EBI_GENIO2_CONFIG2_OFFS) 221 #define EBI_GENIO2_CONFIG3_OFFS 0x00000A18 222 #define EBI_GENIO2_CONFIG3(base) ((base) + EBI_GENIO2_CONFIG3_OFFS) 223 #define EBI_GENIO3_CONFIG1_OFFS 0x00000A20 224 #define EBI_GENIO3_CONFIG1(base) ((base) + EBI_GENIO3_CONFIG1_OFFS) 225 #define EBI_GENIO3_CONFIG2_OFFS 0x00000A24 226 #define EBI_GENIO3_CONFIG2(base) ((base) + EBI_GENIO3_CONFIG2_OFFS) 227 #define EBI_GENIO3_CONFIG3_OFFS 0x00000A28 228 #define EBI_GENIO3_CONFIG3(base) ((base) + EBI_GENIO3_CONFIG3_OFFS) 229 #define EBI_GENIO4_CONFIG1_OFFS 0x00000A30 230 #define EBI_GENIO4_CONFIG1(base) ((base) + EBI_GENIO4_CONFIG1_OFFS) 231 #define EBI_GENIO4_CONFIG2_OFFS 0x00000A34 232 #define EBI_GENIO4_CONFIG2(base) ((base) + EBI_GENIO4_CONFIG2_OFFS) 233 #define EBI_GENIO4_CONFIG3_OFFS 0x00000A38 234 #define EBI_GENIO4_CONFIG3(base) ((base) + EBI_GENIO4_CONFIG3_OFFS) 235 #define EBI_GENIO5_CONFIG1_OFFS 0x00000A40 236 #define EBI_GENIO5_CONFIG1(base) ((base) + EBI_GENIO5_CONFIG1_OFFS) 237 #define EBI_GENIO5_CONFIG2_OFFS 0x00000A44 238 #define EBI_GENIO5_CONFIG2(base) ((base) + EBI_GENIO5_CONFIG2_OFFS) 239 #define EBI_GENIO5_CONFIG3_OFFS 0x00000A48 240 #define EBI_GENIO5_CONFIG3(base) ((base) + EBI_GENIO5_CONFIG3_OFFS) 241 242 #endif 243