1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering 4 * 5 * Copyright (C) 2006 Micronas GmbH 6 */ 7 8 #include <common.h> 9 #include "vct.h" 10 11 typedef union _TOP_PINMUX_t 12 { 13 u32 reg; 14 struct { 15 u32 res : 24; /* reserved */ 16 u32 drive : 2; /* Driver strength */ 17 u32 slew : 1; /* Slew rate */ 18 u32 strig : 1; /* Schmitt trigger input*/ 19 u32 pu_pd : 2; /* Pull up/ pull down */ 20 u32 funsel : 2; /* Pin function */ 21 } Bits; 22 } TOP_PINMUX_t; 23 24 #if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM) 25 26 static TOP_PINMUX_t top_read_pin(int pin) 27 { 28 TOP_PINMUX_t reg; 29 30 switch (pin) { 31 case 2: 32 case 3: 33 case 6: 34 case 9: 35 reg.reg = 0xdeadbeef; 36 break; 37 case 4: 38 reg.reg = reg_read(FWSRAM_TOP_SCL_CFG(FWSRAM_BASE)); 39 break; 40 case 5: 41 reg.reg = reg_read(FWSRAM_TOP_SDA_CFG(FWSRAM_BASE)); 42 break; 43 case 7: 44 reg.reg = reg_read(FWSRAM_TOP_TDO_CFG(FWSRAM_BASE)); 45 break; 46 case 8: 47 reg.reg = reg_read(FWSRAM_TOP_GPIO2_0_CFG(FWSRAM_BASE)); 48 break; 49 case 10: 50 case 11: 51 case 12: 52 case 13: 53 case 14: 54 case 15: 55 case 16: 56 reg.reg = reg_read(FWSRAM_BASE + FWSRAM_TOP_GPIO2_1_CFG_OFFS + 57 ((pin - 10) * 4)); 58 break; 59 default: 60 reg.reg = reg_read(TOP_BASE + (pin * 4)); 61 break; 62 } 63 64 return reg; 65 } 66 67 static void top_write_pin(int pin, TOP_PINMUX_t reg) 68 { 69 70 switch (pin) { 71 case 4: 72 reg_write(FWSRAM_TOP_SCL_CFG(FWSRAM_BASE), reg.reg); 73 break; 74 case 5: 75 reg_write(FWSRAM_TOP_SDA_CFG(FWSRAM_BASE), reg.reg); 76 break; 77 case 7: 78 reg_write(FWSRAM_TOP_TDO_CFG(FWSRAM_BASE), reg.reg); 79 break; 80 case 8: 81 reg_write(FWSRAM_TOP_GPIO2_0_CFG(FWSRAM_BASE), reg.reg); 82 break; 83 case 10: 84 case 11: 85 case 12: 86 case 13: 87 case 14: 88 case 15: 89 case 16: 90 reg_write(FWSRAM_BASE + FWSRAM_TOP_GPIO2_1_CFG_OFFS + 91 ((pin - 10) * 4), reg.reg); 92 break; 93 default: 94 reg_write(TOP_BASE + (pin * 4), reg.reg); 95 break; 96 } 97 } 98 99 int top_set_pin(int pin, int func) 100 { 101 TOP_PINMUX_t reg; 102 103 /* check global range */ 104 if ((pin < 0) || (pin > 170) || (func < 0) || (func > 3)) 105 return -1; /* pin number or function out of valid range */ 106 107 /* check undefined values; */ 108 if ((pin == 2) || (pin == 3) || (pin == 6) || (pin == 9)) 109 return -1; /* pin number out of valid range */ 110 111 reg = top_read_pin(pin); 112 reg.Bits.funsel = func; 113 top_write_pin(pin, reg); 114 115 return 0; 116 } 117 118 #endif 119 120 #if defined(CONFIG_VCT_PLATINUMAVC) 121 122 int top_set_pin(int pin, int func) 123 { 124 TOP_PINMUX_t reg; 125 126 /* check global range */ 127 if ((pin < 0) || (pin > 158)) 128 return -1; /* pin number or function out of valid range */ 129 130 reg.reg = reg_read(TOP_BASE + (pin * 4)); 131 reg.Bits.funsel = func; 132 reg_write(TOP_BASE + (pin * 4), reg.reg); 133 134 return 0; 135 } 136 137 #endif 138 139 void vct_pin_mux_initialize(void) 140 { 141 #if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM) 142 top_set_pin(34, 01); /* EBI_CS0 */ 143 top_set_pin(33, 01); /* EBI_CS1 */ 144 top_set_pin(32, 01); /* EBI_CS2 */ 145 top_set_pin(100, 02); /* EBI_CS3 */ 146 top_set_pin(101, 02); /* EBI_CS4 */ 147 top_set_pin(102, 02); /* EBI_CS5 */ 148 top_set_pin(103, 02); /* EBI_CS6 */ 149 top_set_pin(104, 02); /* EBI_CS7 top_set_pin(104,03); EBI_GENIO3 */ 150 top_set_pin(35, 01); /* EBI_ALE */ 151 top_set_pin(36, 01); /* EBI_ADDR15 */ 152 top_set_pin(37, 01); /* EBI_ADDR14 top_set_pin(78,03); EBI_ADDR14 */ 153 top_set_pin(38, 01); /* EBI_ADDR13 */ 154 top_set_pin(39, 01); /* EBI_ADDR12 */ 155 top_set_pin(40, 01); /* EBI_ADDR11 */ 156 top_set_pin(41, 01); /* EBI_ADDR10 */ 157 top_set_pin(42, 01); /* EBI_ADDR9 */ 158 top_set_pin(43, 01); /* EBI_ADDR8 */ 159 top_set_pin(44, 01); /* EBI_ADDR7 */ 160 top_set_pin(45, 01); /* EBI_ADDR6 */ 161 top_set_pin(46, 01); /* EBI_ADDR5 */ 162 top_set_pin(47, 01); /* EBI_ADDR4 */ 163 top_set_pin(48, 01); /* EBI_ADDR3 */ 164 top_set_pin(49, 01); /* EBI_ADDR2 */ 165 top_set_pin(50, 01); /* EBI_ADDR1 */ 166 top_set_pin(51, 01); /* EBI_ADDR0 */ 167 top_set_pin(52, 01); /* EBI_DIR */ 168 top_set_pin(53, 01); /* EBI_DAT15 top_set_pin(81,01); EBI_DAT15 */ 169 top_set_pin(54, 01); /* EBI_DAT14 top_set_pin(82,01); EBI_DAT14 */ 170 top_set_pin(55, 01); /* EBI_DAT13 top_set_pin(83,01); EBI_DAT13 */ 171 top_set_pin(56, 01); /* EBI_DAT12 top_set_pin(84,01); EBI_DAT12 */ 172 top_set_pin(57, 01); /* EBI_DAT11 top_set_pin(85,01); EBI_DAT11 */ 173 top_set_pin(58, 01); /* EBI_DAT10 top_set_pin(86,01); EBI_DAT10 */ 174 top_set_pin(59, 01); /* EBI_DAT9 top_set_pin(87,01); EBI_DAT9 */ 175 top_set_pin(60, 01); /* EBI_DAT8 top_set_pin(88,01); EBI_DAT8 */ 176 top_set_pin(61, 01); /* EBI_DAT7 */ 177 top_set_pin(62, 01); /* EBI_DAT6 */ 178 top_set_pin(63, 01); /* EBI_DAT5 */ 179 top_set_pin(64, 01); /* EBI_DAT4 */ 180 top_set_pin(65, 01); /* EBI_DAT3 */ 181 top_set_pin(66, 01); /* EBI_DAT2 */ 182 top_set_pin(67, 01); /* EBI_DAT1 */ 183 top_set_pin(68, 01); /* EBI_DAT0 */ 184 top_set_pin(69, 01); /* EBI_IORD */ 185 top_set_pin(70, 01); /* EBI_IOWR */ 186 top_set_pin(71, 01); /* EBI_WE */ 187 top_set_pin(72, 01); /* EBI_OE */ 188 top_set_pin(73, 01); /* EBI_IORDY */ 189 top_set_pin(95, 02); /* EBI_EBI_DMACK*/ 190 top_set_pin(112, 02); /* EBI_IRQ0 */ 191 top_set_pin(111, 02); /* EBI_IRQ1 top_set_pin(111,03); EBI_DMARQ */ 192 top_set_pin(107, 02); /* EBI_IRQ2 */ 193 top_set_pin(108, 02); /* EBI_IRQ3 */ 194 top_set_pin(30, 01); /* EBI_GENIO1 top_set_pin(99,03); EBI_GENIO1 */ 195 top_set_pin(31, 01); /* EBI_GENIO2 top_set_pin(98,03); EBI_GENIO2 */ 196 top_set_pin(105, 02); /* EBI_GENIO3 top_set_pin(104,03); EBI_GENIO3 */ 197 top_set_pin(106, 02); /* EBI_GENIO4 top_set_pin(144,02); EBI_GENIO4 */ 198 top_set_pin(109, 02); /* EBI_GENIO5 top_set_pin(142,02); EBI_GENIO5 */ 199 top_set_pin(110, 02); /* EBI_BURST_CLK */ 200 #endif 201 202 #if defined(CONFIG_VCT_PLATINUMAVC) 203 top_set_pin(19, 01); /* EBI_CS0 */ 204 top_set_pin(18, 01); /* EBI_CS1 */ 205 top_set_pin(17, 01); /* EBI_CS2 */ 206 top_set_pin(92, 02); /* EBI_CS3 */ 207 top_set_pin(93, 02); /* EBI_CS4 */ 208 top_set_pin(95, 02); /* EBI_CS6 */ 209 top_set_pin(96, 02); /* EBI_CS7 top_set_pin(104,03); EBI_GENIO3 */ 210 top_set_pin(20, 01); /* EBI_ALE */ 211 top_set_pin(21, 01); /* EBI_ADDR15 */ 212 top_set_pin(22, 01); /* EBI_ADDR14 top_set_pin(78,03); EBI_ADDR14 */ 213 top_set_pin(23, 01); /* EBI_ADDR13 */ 214 top_set_pin(24, 01); /* EBI_ADDR12 */ 215 top_set_pin(25, 01); /* EBI_ADDR11 */ 216 top_set_pin(26, 01); /* EBI_ADDR10 */ 217 top_set_pin(27, 01); /* EBI_ADDR9 */ 218 top_set_pin(28, 01); /* EBI_ADDR8 */ 219 top_set_pin(29, 01); /* EBI_ADDR7 */ 220 top_set_pin(30, 01); /* EBI_ADDR6 */ 221 top_set_pin(31, 01); /* EBI_ADDR5 */ 222 top_set_pin(32, 01); /* EBI_ADDR4 */ 223 top_set_pin(33, 01); /* EBI_ADDR3 */ 224 top_set_pin(34, 01); /* EBI_ADDR2 */ 225 top_set_pin(35, 01); /* EBI_ADDR1 */ 226 top_set_pin(36, 01); /* EBI_ADDR0 */ 227 top_set_pin(37, 01); /* EBI_DIR */ 228 top_set_pin(38, 01); /* EBI_DAT15 top_set_pin(81,01); EBI_DAT15 */ 229 top_set_pin(39, 01); /* EBI_DAT14 top_set_pin(82,01); EBI_DAT14 */ 230 top_set_pin(40, 01); /* EBI_DAT13 top_set_pin(83,01); EBI_DAT13 */ 231 top_set_pin(41, 01); /* EBI_DAT12 top_set_pin(84,01); EBI_DAT12 */ 232 top_set_pin(42, 01); /* EBI_DAT11 top_set_pin(85,01); EBI_DAT11 */ 233 top_set_pin(43, 01); /* EBI_DAT10 top_set_pin(86,01); EBI_DAT10 */ 234 top_set_pin(44, 01); /* EBI_DAT9 top_set_pin(87,01); EBI_DAT9 */ 235 top_set_pin(45, 01); /* EBI_DAT8 top_set_pin(88,01); EBI_DAT8 */ 236 top_set_pin(46, 01); /* EBI_DAT7 */ 237 top_set_pin(47, 01); /* EBI_DAT6 */ 238 top_set_pin(48, 01); /* EBI_DAT5 */ 239 top_set_pin(49, 01); /* EBI_DAT4 */ 240 top_set_pin(50, 01); /* EBI_DAT3 */ 241 top_set_pin(51, 01); /* EBI_DAT2 */ 242 top_set_pin(52, 01); /* EBI_DAT1 */ 243 top_set_pin(53, 01); /* EBI_DAT0 */ 244 top_set_pin(54, 01); /* EBI_IORD */ 245 top_set_pin(55, 01); /* EBI_IOWR */ 246 top_set_pin(56, 01); /* EBI_WE */ 247 top_set_pin(57, 01); /* EBI_OE */ 248 top_set_pin(58, 01); /* EBI_IORDY */ 249 top_set_pin(87, 02); /* EBI_EBI_DMACK*/ 250 top_set_pin(106, 02); /* EBI_IRQ0 */ 251 top_set_pin(105, 02); /* EBI_IRQ1 top_set_pin(111,03); EBI_DMARQ */ 252 top_set_pin(101, 02); /* EBI_IRQ2 */ 253 top_set_pin(102, 02); /* EBI_IRQ3 */ 254 top_set_pin(15, 01); /* EBI_GENIO1 top_set_pin(99,03); EBI_GENIO1 */ 255 top_set_pin(16, 01); /* EBI_GENIO2 top_set_pin(98,03); EBI_GENIO2 */ 256 top_set_pin(99, 02); /* EBI_GENIO3 top_set_pin(104,03); EBI_GENIO3 */ 257 top_set_pin(100, 02); /* EBI_GENIO4 top_set_pin(144,02); EBI_GENIO4 */ 258 top_set_pin(103, 02); /* EBI_GENIO5 top_set_pin(142,02); EBI_GENIO5 */ 259 top_set_pin(104, 02); /* EBI_BURST_CLK */ 260 #endif 261 262 /* I2C: Configure I2C-2 as GPIO to enable soft-i2c */ 263 top_set_pin(0, 2); /* SCL2 on GPIO 11 */ 264 top_set_pin(1, 2); /* SDA2 on GPIO 10 */ 265 266 /* UART pins */ 267 #if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM) 268 top_set_pin(141, 1); 269 top_set_pin(143, 1); 270 #endif 271 #if defined(CONFIG_VCT_PLATINUMAVC) 272 top_set_pin(107, 1); 273 top_set_pin(109, 1); 274 #endif 275 } 276