1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2ae691e57SStefan Roese /*
3ae691e57SStefan Roese * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
4ae691e57SStefan Roese *
5ae691e57SStefan Roese * Copyright (C) 2006 Micronas GmbH
6ae691e57SStefan Roese */
7ae691e57SStefan Roese
8ae691e57SStefan Roese #include <common.h>
9ae691e57SStefan Roese #include "vct.h"
10ae691e57SStefan Roese
11ae691e57SStefan Roese typedef union _TOP_PINMUX_t
12ae691e57SStefan Roese {
13ae691e57SStefan Roese u32 reg;
14ae691e57SStefan Roese struct {
15ae691e57SStefan Roese u32 res : 24; /* reserved */
16ae691e57SStefan Roese u32 drive : 2; /* Driver strength */
17ae691e57SStefan Roese u32 slew : 1; /* Slew rate */
18ae691e57SStefan Roese u32 strig : 1; /* Schmitt trigger input*/
19ae691e57SStefan Roese u32 pu_pd : 2; /* Pull up/ pull down */
20ae691e57SStefan Roese u32 funsel : 2; /* Pin function */
21ae691e57SStefan Roese } Bits;
22ae691e57SStefan Roese } TOP_PINMUX_t;
23ae691e57SStefan Roese
24ae691e57SStefan Roese #if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
25ae691e57SStefan Roese
top_read_pin(int pin)26ae691e57SStefan Roese static TOP_PINMUX_t top_read_pin(int pin)
27ae691e57SStefan Roese {
28ae691e57SStefan Roese TOP_PINMUX_t reg;
29ae691e57SStefan Roese
30ae691e57SStefan Roese switch (pin) {
31ae691e57SStefan Roese case 2:
32ae691e57SStefan Roese case 3:
33ae691e57SStefan Roese case 6:
34ae691e57SStefan Roese case 9:
35ae691e57SStefan Roese reg.reg = 0xdeadbeef;
36ae691e57SStefan Roese break;
37ae691e57SStefan Roese case 4:
38ae691e57SStefan Roese reg.reg = reg_read(FWSRAM_TOP_SCL_CFG(FWSRAM_BASE));
39ae691e57SStefan Roese break;
40ae691e57SStefan Roese case 5:
41ae691e57SStefan Roese reg.reg = reg_read(FWSRAM_TOP_SDA_CFG(FWSRAM_BASE));
42ae691e57SStefan Roese break;
43ae691e57SStefan Roese case 7:
44ae691e57SStefan Roese reg.reg = reg_read(FWSRAM_TOP_TDO_CFG(FWSRAM_BASE));
45ae691e57SStefan Roese break;
46ae691e57SStefan Roese case 8:
47ae691e57SStefan Roese reg.reg = reg_read(FWSRAM_TOP_GPIO2_0_CFG(FWSRAM_BASE));
48ae691e57SStefan Roese break;
49ae691e57SStefan Roese case 10:
50ae691e57SStefan Roese case 11:
51ae691e57SStefan Roese case 12:
52ae691e57SStefan Roese case 13:
53ae691e57SStefan Roese case 14:
54ae691e57SStefan Roese case 15:
55ae691e57SStefan Roese case 16:
56ae691e57SStefan Roese reg.reg = reg_read(FWSRAM_BASE + FWSRAM_TOP_GPIO2_1_CFG_OFFS +
57ae691e57SStefan Roese ((pin - 10) * 4));
58ae691e57SStefan Roese break;
59ae691e57SStefan Roese default:
60ae691e57SStefan Roese reg.reg = reg_read(TOP_BASE + (pin * 4));
61ae691e57SStefan Roese break;
62ae691e57SStefan Roese }
63ae691e57SStefan Roese
64ae691e57SStefan Roese return reg;
65ae691e57SStefan Roese }
66ae691e57SStefan Roese
top_write_pin(int pin,TOP_PINMUX_t reg)67ae691e57SStefan Roese static void top_write_pin(int pin, TOP_PINMUX_t reg)
68ae691e57SStefan Roese {
69ae691e57SStefan Roese
70ae691e57SStefan Roese switch (pin) {
71ae691e57SStefan Roese case 4:
72ae691e57SStefan Roese reg_write(FWSRAM_TOP_SCL_CFG(FWSRAM_BASE), reg.reg);
73ae691e57SStefan Roese break;
74ae691e57SStefan Roese case 5:
75ae691e57SStefan Roese reg_write(FWSRAM_TOP_SDA_CFG(FWSRAM_BASE), reg.reg);
76ae691e57SStefan Roese break;
77ae691e57SStefan Roese case 7:
78ae691e57SStefan Roese reg_write(FWSRAM_TOP_TDO_CFG(FWSRAM_BASE), reg.reg);
79ae691e57SStefan Roese break;
80ae691e57SStefan Roese case 8:
81ae691e57SStefan Roese reg_write(FWSRAM_TOP_GPIO2_0_CFG(FWSRAM_BASE), reg.reg);
82ae691e57SStefan Roese break;
83ae691e57SStefan Roese case 10:
84ae691e57SStefan Roese case 11:
85ae691e57SStefan Roese case 12:
86ae691e57SStefan Roese case 13:
87ae691e57SStefan Roese case 14:
88ae691e57SStefan Roese case 15:
89ae691e57SStefan Roese case 16:
90ae691e57SStefan Roese reg_write(FWSRAM_BASE + FWSRAM_TOP_GPIO2_1_CFG_OFFS +
91ae691e57SStefan Roese ((pin - 10) * 4), reg.reg);
92ae691e57SStefan Roese break;
93ae691e57SStefan Roese default:
94ae691e57SStefan Roese reg_write(TOP_BASE + (pin * 4), reg.reg);
95ae691e57SStefan Roese break;
96ae691e57SStefan Roese }
97ae691e57SStefan Roese }
98ae691e57SStefan Roese
top_set_pin(int pin,int func)99ae691e57SStefan Roese int top_set_pin(int pin, int func)
100ae691e57SStefan Roese {
101ae691e57SStefan Roese TOP_PINMUX_t reg;
102ae691e57SStefan Roese
103ae691e57SStefan Roese /* check global range */
104ae691e57SStefan Roese if ((pin < 0) || (pin > 170) || (func < 0) || (func > 3))
105ae691e57SStefan Roese return -1; /* pin number or function out of valid range */
106ae691e57SStefan Roese
107ae691e57SStefan Roese /* check undefined values; */
108ae691e57SStefan Roese if ((pin == 2) || (pin == 3) || (pin == 6) || (pin == 9))
109ae691e57SStefan Roese return -1; /* pin number out of valid range */
110ae691e57SStefan Roese
111ae691e57SStefan Roese reg = top_read_pin(pin);
112ae691e57SStefan Roese reg.Bits.funsel = func;
113ae691e57SStefan Roese top_write_pin(pin, reg);
114ae691e57SStefan Roese
115ae691e57SStefan Roese return 0;
116ae691e57SStefan Roese }
117ae691e57SStefan Roese
118ae691e57SStefan Roese #endif
119ae691e57SStefan Roese
120ae691e57SStefan Roese #if defined(CONFIG_VCT_PLATINUMAVC)
121ae691e57SStefan Roese
top_set_pin(int pin,int func)122ae691e57SStefan Roese int top_set_pin(int pin, int func)
123ae691e57SStefan Roese {
124ae691e57SStefan Roese TOP_PINMUX_t reg;
125ae691e57SStefan Roese
126ae691e57SStefan Roese /* check global range */
127ae691e57SStefan Roese if ((pin < 0) || (pin > 158))
128ae691e57SStefan Roese return -1; /* pin number or function out of valid range */
129ae691e57SStefan Roese
130ae691e57SStefan Roese reg.reg = reg_read(TOP_BASE + (pin * 4));
131ae691e57SStefan Roese reg.Bits.funsel = func;
132ae691e57SStefan Roese reg_write(TOP_BASE + (pin * 4), reg.reg);
133ae691e57SStefan Roese
134ae691e57SStefan Roese return 0;
135ae691e57SStefan Roese }
136ae691e57SStefan Roese
137ae691e57SStefan Roese #endif
138ae691e57SStefan Roese
vct_pin_mux_initialize(void)139ae691e57SStefan Roese void vct_pin_mux_initialize(void)
140ae691e57SStefan Roese {
141ae691e57SStefan Roese #if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
142ae691e57SStefan Roese top_set_pin(34, 01); /* EBI_CS0 */
143ae691e57SStefan Roese top_set_pin(33, 01); /* EBI_CS1 */
144ae691e57SStefan Roese top_set_pin(32, 01); /* EBI_CS2 */
145ae691e57SStefan Roese top_set_pin(100, 02); /* EBI_CS3 */
146ae691e57SStefan Roese top_set_pin(101, 02); /* EBI_CS4 */
147ae691e57SStefan Roese top_set_pin(102, 02); /* EBI_CS5 */
148ae691e57SStefan Roese top_set_pin(103, 02); /* EBI_CS6 */
149ae691e57SStefan Roese top_set_pin(104, 02); /* EBI_CS7 top_set_pin(104,03); EBI_GENIO3 */
150ae691e57SStefan Roese top_set_pin(35, 01); /* EBI_ALE */
151ae691e57SStefan Roese top_set_pin(36, 01); /* EBI_ADDR15 */
152ae691e57SStefan Roese top_set_pin(37, 01); /* EBI_ADDR14 top_set_pin(78,03); EBI_ADDR14 */
153ae691e57SStefan Roese top_set_pin(38, 01); /* EBI_ADDR13 */
154ae691e57SStefan Roese top_set_pin(39, 01); /* EBI_ADDR12 */
155ae691e57SStefan Roese top_set_pin(40, 01); /* EBI_ADDR11 */
156ae691e57SStefan Roese top_set_pin(41, 01); /* EBI_ADDR10 */
157ae691e57SStefan Roese top_set_pin(42, 01); /* EBI_ADDR9 */
158ae691e57SStefan Roese top_set_pin(43, 01); /* EBI_ADDR8 */
159ae691e57SStefan Roese top_set_pin(44, 01); /* EBI_ADDR7 */
160ae691e57SStefan Roese top_set_pin(45, 01); /* EBI_ADDR6 */
161ae691e57SStefan Roese top_set_pin(46, 01); /* EBI_ADDR5 */
162ae691e57SStefan Roese top_set_pin(47, 01); /* EBI_ADDR4 */
163ae691e57SStefan Roese top_set_pin(48, 01); /* EBI_ADDR3 */
164ae691e57SStefan Roese top_set_pin(49, 01); /* EBI_ADDR2 */
165ae691e57SStefan Roese top_set_pin(50, 01); /* EBI_ADDR1 */
166ae691e57SStefan Roese top_set_pin(51, 01); /* EBI_ADDR0 */
167ae691e57SStefan Roese top_set_pin(52, 01); /* EBI_DIR */
168ae691e57SStefan Roese top_set_pin(53, 01); /* EBI_DAT15 top_set_pin(81,01); EBI_DAT15 */
169ae691e57SStefan Roese top_set_pin(54, 01); /* EBI_DAT14 top_set_pin(82,01); EBI_DAT14 */
170ae691e57SStefan Roese top_set_pin(55, 01); /* EBI_DAT13 top_set_pin(83,01); EBI_DAT13 */
171ae691e57SStefan Roese top_set_pin(56, 01); /* EBI_DAT12 top_set_pin(84,01); EBI_DAT12 */
172ae691e57SStefan Roese top_set_pin(57, 01); /* EBI_DAT11 top_set_pin(85,01); EBI_DAT11 */
173ae691e57SStefan Roese top_set_pin(58, 01); /* EBI_DAT10 top_set_pin(86,01); EBI_DAT10 */
174ae691e57SStefan Roese top_set_pin(59, 01); /* EBI_DAT9 top_set_pin(87,01); EBI_DAT9 */
175ae691e57SStefan Roese top_set_pin(60, 01); /* EBI_DAT8 top_set_pin(88,01); EBI_DAT8 */
176ae691e57SStefan Roese top_set_pin(61, 01); /* EBI_DAT7 */
177ae691e57SStefan Roese top_set_pin(62, 01); /* EBI_DAT6 */
178ae691e57SStefan Roese top_set_pin(63, 01); /* EBI_DAT5 */
179ae691e57SStefan Roese top_set_pin(64, 01); /* EBI_DAT4 */
180ae691e57SStefan Roese top_set_pin(65, 01); /* EBI_DAT3 */
181ae691e57SStefan Roese top_set_pin(66, 01); /* EBI_DAT2 */
182ae691e57SStefan Roese top_set_pin(67, 01); /* EBI_DAT1 */
183ae691e57SStefan Roese top_set_pin(68, 01); /* EBI_DAT0 */
184ae691e57SStefan Roese top_set_pin(69, 01); /* EBI_IORD */
185ae691e57SStefan Roese top_set_pin(70, 01); /* EBI_IOWR */
186ae691e57SStefan Roese top_set_pin(71, 01); /* EBI_WE */
187ae691e57SStefan Roese top_set_pin(72, 01); /* EBI_OE */
188ae691e57SStefan Roese top_set_pin(73, 01); /* EBI_IORDY */
189ae691e57SStefan Roese top_set_pin(95, 02); /* EBI_EBI_DMACK*/
190ae691e57SStefan Roese top_set_pin(112, 02); /* EBI_IRQ0 */
191ae691e57SStefan Roese top_set_pin(111, 02); /* EBI_IRQ1 top_set_pin(111,03); EBI_DMARQ */
192ae691e57SStefan Roese top_set_pin(107, 02); /* EBI_IRQ2 */
193ae691e57SStefan Roese top_set_pin(108, 02); /* EBI_IRQ3 */
194ae691e57SStefan Roese top_set_pin(30, 01); /* EBI_GENIO1 top_set_pin(99,03); EBI_GENIO1 */
195ae691e57SStefan Roese top_set_pin(31, 01); /* EBI_GENIO2 top_set_pin(98,03); EBI_GENIO2 */
196ae691e57SStefan Roese top_set_pin(105, 02); /* EBI_GENIO3 top_set_pin(104,03); EBI_GENIO3 */
197ae691e57SStefan Roese top_set_pin(106, 02); /* EBI_GENIO4 top_set_pin(144,02); EBI_GENIO4 */
198ae691e57SStefan Roese top_set_pin(109, 02); /* EBI_GENIO5 top_set_pin(142,02); EBI_GENIO5 */
199ae691e57SStefan Roese top_set_pin(110, 02); /* EBI_BURST_CLK */
200ae691e57SStefan Roese #endif
201ae691e57SStefan Roese
202ae691e57SStefan Roese #if defined(CONFIG_VCT_PLATINUMAVC)
203ae691e57SStefan Roese top_set_pin(19, 01); /* EBI_CS0 */
204ae691e57SStefan Roese top_set_pin(18, 01); /* EBI_CS1 */
205ae691e57SStefan Roese top_set_pin(17, 01); /* EBI_CS2 */
206ae691e57SStefan Roese top_set_pin(92, 02); /* EBI_CS3 */
207ae691e57SStefan Roese top_set_pin(93, 02); /* EBI_CS4 */
208ae691e57SStefan Roese top_set_pin(95, 02); /* EBI_CS6 */
209ae691e57SStefan Roese top_set_pin(96, 02); /* EBI_CS7 top_set_pin(104,03); EBI_GENIO3 */
210ae691e57SStefan Roese top_set_pin(20, 01); /* EBI_ALE */
211ae691e57SStefan Roese top_set_pin(21, 01); /* EBI_ADDR15 */
212ae691e57SStefan Roese top_set_pin(22, 01); /* EBI_ADDR14 top_set_pin(78,03); EBI_ADDR14 */
213ae691e57SStefan Roese top_set_pin(23, 01); /* EBI_ADDR13 */
214ae691e57SStefan Roese top_set_pin(24, 01); /* EBI_ADDR12 */
215ae691e57SStefan Roese top_set_pin(25, 01); /* EBI_ADDR11 */
216ae691e57SStefan Roese top_set_pin(26, 01); /* EBI_ADDR10 */
217ae691e57SStefan Roese top_set_pin(27, 01); /* EBI_ADDR9 */
218ae691e57SStefan Roese top_set_pin(28, 01); /* EBI_ADDR8 */
219ae691e57SStefan Roese top_set_pin(29, 01); /* EBI_ADDR7 */
220ae691e57SStefan Roese top_set_pin(30, 01); /* EBI_ADDR6 */
221ae691e57SStefan Roese top_set_pin(31, 01); /* EBI_ADDR5 */
222ae691e57SStefan Roese top_set_pin(32, 01); /* EBI_ADDR4 */
223ae691e57SStefan Roese top_set_pin(33, 01); /* EBI_ADDR3 */
224ae691e57SStefan Roese top_set_pin(34, 01); /* EBI_ADDR2 */
225ae691e57SStefan Roese top_set_pin(35, 01); /* EBI_ADDR1 */
226ae691e57SStefan Roese top_set_pin(36, 01); /* EBI_ADDR0 */
227ae691e57SStefan Roese top_set_pin(37, 01); /* EBI_DIR */
228ae691e57SStefan Roese top_set_pin(38, 01); /* EBI_DAT15 top_set_pin(81,01); EBI_DAT15 */
229ae691e57SStefan Roese top_set_pin(39, 01); /* EBI_DAT14 top_set_pin(82,01); EBI_DAT14 */
230ae691e57SStefan Roese top_set_pin(40, 01); /* EBI_DAT13 top_set_pin(83,01); EBI_DAT13 */
231ae691e57SStefan Roese top_set_pin(41, 01); /* EBI_DAT12 top_set_pin(84,01); EBI_DAT12 */
232ae691e57SStefan Roese top_set_pin(42, 01); /* EBI_DAT11 top_set_pin(85,01); EBI_DAT11 */
233ae691e57SStefan Roese top_set_pin(43, 01); /* EBI_DAT10 top_set_pin(86,01); EBI_DAT10 */
234ae691e57SStefan Roese top_set_pin(44, 01); /* EBI_DAT9 top_set_pin(87,01); EBI_DAT9 */
235ae691e57SStefan Roese top_set_pin(45, 01); /* EBI_DAT8 top_set_pin(88,01); EBI_DAT8 */
236ae691e57SStefan Roese top_set_pin(46, 01); /* EBI_DAT7 */
237ae691e57SStefan Roese top_set_pin(47, 01); /* EBI_DAT6 */
238ae691e57SStefan Roese top_set_pin(48, 01); /* EBI_DAT5 */
239ae691e57SStefan Roese top_set_pin(49, 01); /* EBI_DAT4 */
240ae691e57SStefan Roese top_set_pin(50, 01); /* EBI_DAT3 */
241ae691e57SStefan Roese top_set_pin(51, 01); /* EBI_DAT2 */
242ae691e57SStefan Roese top_set_pin(52, 01); /* EBI_DAT1 */
243ae691e57SStefan Roese top_set_pin(53, 01); /* EBI_DAT0 */
244ae691e57SStefan Roese top_set_pin(54, 01); /* EBI_IORD */
245ae691e57SStefan Roese top_set_pin(55, 01); /* EBI_IOWR */
246ae691e57SStefan Roese top_set_pin(56, 01); /* EBI_WE */
247ae691e57SStefan Roese top_set_pin(57, 01); /* EBI_OE */
248ae691e57SStefan Roese top_set_pin(58, 01); /* EBI_IORDY */
249ae691e57SStefan Roese top_set_pin(87, 02); /* EBI_EBI_DMACK*/
250ae691e57SStefan Roese top_set_pin(106, 02); /* EBI_IRQ0 */
251ae691e57SStefan Roese top_set_pin(105, 02); /* EBI_IRQ1 top_set_pin(111,03); EBI_DMARQ */
252ae691e57SStefan Roese top_set_pin(101, 02); /* EBI_IRQ2 */
253ae691e57SStefan Roese top_set_pin(102, 02); /* EBI_IRQ3 */
254ae691e57SStefan Roese top_set_pin(15, 01); /* EBI_GENIO1 top_set_pin(99,03); EBI_GENIO1 */
255ae691e57SStefan Roese top_set_pin(16, 01); /* EBI_GENIO2 top_set_pin(98,03); EBI_GENIO2 */
256ae691e57SStefan Roese top_set_pin(99, 02); /* EBI_GENIO3 top_set_pin(104,03); EBI_GENIO3 */
257ae691e57SStefan Roese top_set_pin(100, 02); /* EBI_GENIO4 top_set_pin(144,02); EBI_GENIO4 */
258ae691e57SStefan Roese top_set_pin(103, 02); /* EBI_GENIO5 top_set_pin(142,02); EBI_GENIO5 */
259ae691e57SStefan Roese top_set_pin(104, 02); /* EBI_BURST_CLK */
260ae691e57SStefan Roese #endif
261ae691e57SStefan Roese
262ae691e57SStefan Roese /* I2C: Configure I2C-2 as GPIO to enable soft-i2c */
263ae691e57SStefan Roese top_set_pin(0, 2); /* SCL2 on GPIO 11 */
264ae691e57SStefan Roese top_set_pin(1, 2); /* SDA2 on GPIO 10 */
265ae691e57SStefan Roese
266ae691e57SStefan Roese /* UART pins */
267ae691e57SStefan Roese #if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
268ae691e57SStefan Roese top_set_pin(141, 1);
269ae691e57SStefan Roese top_set_pin(143, 1);
270ae691e57SStefan Roese #endif
271ae691e57SStefan Roese #if defined(CONFIG_VCT_PLATINUMAVC)
272ae691e57SStefan Roese top_set_pin(107, 1);
273ae691e57SStefan Roese top_set_pin(109, 1);
274ae691e57SStefan Roese #endif
275ae691e57SStefan Roese }
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