1 /* 2 * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <linux/mtd/mtd.h> 10 #include <linux/mtd/onenand.h> 11 #include "vct.h" 12 13 #define BURST_SIZE_WORDS 4 14 15 static u16 ebi_nand_read_word(void __iomem *addr) 16 { 17 reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_2 | (u32)addr)); 18 ebi_wait(); 19 20 return reg_read(EBI_IO_ACCS_DATA(EBI_BASE)) >> 16; 21 } 22 23 static void ebi_nand_write_word(u16 data, void __iomem * addr) 24 { 25 ebi_wait(); 26 reg_write(EBI_IO_ACCS_DATA(EBI_BASE), (data << 16)); 27 reg_write(EBI_CPU_IO_ACCS(EBI_BASE), 28 EXT_DEVICE_CHANNEL_2 | EBI_CPU_WRITE | (u32)addr); 29 ebi_wait(); 30 } 31 32 /* 33 * EBI initialization for OneNAND FLASH access 34 */ 35 int ebi_init_onenand(void) 36 { 37 reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x83000); 38 39 reg_write(EBI_DEV2_CONFIG1(EBI_BASE), 0x00403002); 40 reg_write(EBI_DEV2_CONFIG2(EBI_BASE), 0x50); 41 42 reg_write(EBI_DEV3_CONFIG1(EBI_BASE), 0x00403002); 43 reg_write(EBI_DEV3_CONFIG2(EBI_BASE), 0x0); /* byte/word ordering */ 44 45 reg_write(EBI_DEV2_TIM1_RD1(EBI_BASE), 0x00504000); 46 reg_write(EBI_DEV2_TIM1_RD2(EBI_BASE), 0x00001000); 47 reg_write(EBI_DEV2_TIM1_WR1(EBI_BASE), 0x12002223); 48 reg_write(EBI_DEV2_TIM1_WR2(EBI_BASE), 0x3FC02220); 49 reg_write(EBI_DEV3_TIM1_RD1(EBI_BASE), 0x00504000); 50 reg_write(EBI_DEV3_TIM1_RD2(EBI_BASE), 0x00001000); 51 reg_write(EBI_DEV3_TIM1_WR1(EBI_BASE), 0x05001000); 52 reg_write(EBI_DEV3_TIM1_WR2(EBI_BASE), 0x00010200); 53 54 reg_write(EBI_DEV2_TIM_EXT(EBI_BASE), 0xFFF00000); 55 reg_write(EBI_DEV2_EXT_ACC(EBI_BASE), 0x0FFFFFFF); 56 57 reg_write(EBI_DEV3_TIM_EXT(EBI_BASE), 0xFFF00000); 58 reg_write(EBI_DEV3_EXT_ACC(EBI_BASE), 0x0FFFFFFF); 59 60 /* prepare DMA configuration for EBI */ 61 reg_write(EBI_DEV3_FIFO_CONFIG(EBI_BASE), 0x0101ff00); 62 63 /* READ only no byte order change, TAG 1 used */ 64 reg_write(EBI_DEV3_DMA_CONFIG2(EBI_BASE), 0x00000004); 65 66 reg_write(EBI_TAG1_SYS_ID(EBI_BASE), 0x0); /* SCC DMA channel 0 */ 67 reg_write(EBI_TAG2_SYS_ID(EBI_BASE), 0x1); 68 reg_write(EBI_TAG3_SYS_ID(EBI_BASE), 0x2); 69 reg_write(EBI_TAG4_SYS_ID(EBI_BASE), 0x3); 70 71 return 0; 72 } 73 74 static void *memcpy_16_from_onenand(void *dst, const void *src, unsigned int len) 75 { 76 void *ret = dst; 77 u16 *d = dst; 78 u16 *s = (u16 *)src; 79 80 len >>= 1; 81 while (len-- > 0) 82 *d++ = ebi_nand_read_word(s++); 83 84 return ret; 85 } 86 87 static void *memcpy_32_from_onenand(void *dst, const void *src, unsigned int len) 88 { 89 void *ret = dst; 90 u32 *d = (u32 *)dst; 91 u32 s = (u32)src; 92 u32 bytes_per_block = BURST_SIZE_WORDS * sizeof(int); 93 u32 n_blocks = len / bytes_per_block; 94 u32 block = 0; 95 u32 burst_word; 96 97 for (block = 0; block < n_blocks; block++) { 98 /* Trigger read channel 3 */ 99 reg_write(EBI_CPU_IO_ACCS(EBI_BASE), 100 (EXT_DEVICE_CHANNEL_3 | (s + (block * bytes_per_block)))); 101 /* Poll status to see whether read has finished */ 102 ebi_wait(); 103 104 /* Squirrel the data away in a safe place */ 105 for (burst_word = 0; burst_word < BURST_SIZE_WORDS; burst_word++) 106 *d++ = reg_read(EBI_IO_ACCS_DATA(EBI_BASE)); 107 } 108 109 return ret; 110 } 111 112 static void *memcpy_16_to_onenand(void *dst, const void *src, unsigned int len) 113 { 114 void *ret = dst; 115 u16 *d = dst; 116 u16 *s = (u16 *)src; 117 118 len >>= 1; 119 while (len-- > 0) 120 ebi_nand_write_word(*s++, d++); 121 122 return ret; 123 } 124 125 static inline int onenand_bufferram_offset(struct mtd_info *mtd, int area) 126 { 127 struct onenand_chip *this = mtd->priv; 128 129 if (ONENAND_CURRENT_BUFFERRAM(this)) { 130 if (area == ONENAND_DATARAM) 131 return mtd->writesize; 132 if (area == ONENAND_SPARERAM) 133 return mtd->oobsize; 134 } 135 136 return 0; 137 } 138 139 static int ebi_read_bufferram(struct mtd_info *mtd, loff_t addr, int area, 140 unsigned char *buffer, int offset, 141 size_t count) 142 { 143 struct onenand_chip *this = mtd->priv; 144 void __iomem *bufferram; 145 146 bufferram = this->base + area; 147 bufferram += onenand_bufferram_offset(mtd, area); 148 149 if (count < 4) 150 memcpy_16_from_onenand(buffer, bufferram + offset, count); 151 else 152 memcpy_32_from_onenand(buffer, bufferram + offset, count); 153 154 return 0; 155 } 156 157 static int ebi_write_bufferram(struct mtd_info *mtd, loff_t addr, int area, 158 const unsigned char *buffer, int offset, 159 size_t count) 160 { 161 struct onenand_chip *this = mtd->priv; 162 void __iomem *bufferram; 163 164 bufferram = this->base + area; 165 bufferram += onenand_bufferram_offset(mtd, area); 166 167 memcpy_16_to_onenand(bufferram + offset, buffer, count); 168 169 return 0; 170 } 171 172 int onenand_board_init(struct mtd_info *mtd) 173 { 174 struct onenand_chip *chip = mtd->priv; 175 176 /* 177 * Insert board specific OneNAND access functions 178 */ 179 chip->read_word = ebi_nand_read_word; 180 chip->write_word = ebi_nand_write_word; 181 182 chip->read_bufferram = ebi_read_bufferram; 183 chip->write_bufferram = ebi_write_bufferram; 184 185 return 0; 186 } 187