xref: /openbmc/u-boot/board/micronas/vct/ebi.h (revision 1e52fea3)
1 /*
2  * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License as
6  * published by the Free Software Foundation; either version 2 of
7  * the License, or (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17  * MA 02111-1307 USA
18  */
19 
20 #ifndef __EBI__
21 #define __EBI__
22 
23 #include <common.h>
24 #include <asm/io.h>
25 #include "vct.h"
26 
27 #define EXT_DEVICE_CHANNEL_3	(0x30000000)
28 #define EXT_DEVICE_CHANNEL_2	(0x20000000)
29 #define EXT_DEVICE_CHANNEL_1	(0x10000000)
30 #define EXT_CPU_ACCESS_ACTIVE	(0x00000001)
31 #define EXT_DMA_ACCESS_ACTIVE	(1 << 14)
32 #define EXT_CPU_IORDY_SL	(0x00000001)
33 
34 #define EBI_CPU_WRITE		(1 << 31)
35 #define EBI_CPU_ID_SHIFT	(28)
36 #define EBI_CPU_ADDR_MASK	~(~0UL << EBI_CPU_ID_SHIFT)
37 
38 /* position of various bit slices in timing register EBI_DEV[01]_TIM1_RD1 */
39 #define ADDR_LATCH_ENABLE	0
40 #define ADDR_ACTIVATION		4
41 #define CHIP_SELECT_START	8
42 #define OUTPUT_ENABLE_START	12
43 #define WAIT_TIME		28
44 #define READ_DURATION		20
45 
46 /* position of various bit slices in timing register EBI_DEV[01]_TIM1_RD2 */
47 #define OUTPUT_ENABLE_END	0
48 #define CHIP_SELECT_END		4
49 #define ADDR_DEACTIVATION	8
50 #define RECOVER_TIME		12
51 #define ACK_TIME		20
52 
53 /* various bits in configuration register EBI_DEV[01]_CONFIG1 */
54 #define EBI_EXTERNAL_DATA_8	(1 <<  8)
55 #define EBI_EXT_ADDR_SHIFT	(1 << 22)
56 #define EBI_EXTERNAL_DATA_16	EBI_EXT_ADDR_SHIFT
57 #define EBI_CHIP_SELECT_1	0x2
58 #define EBI_CHIP_SELECT_2	0x4
59 #define EBI_BUSY_EN_RD		(1 << 12)
60 #define DIR_ACCESS_WRITE	(1 << 20)
61 #define DIR_ACCESS_MASK		(1 << 20)
62 
63 /* various bits in configuration register EBI_DEV[01]_CONFIG2 */
64 #define ADDRESS_INCREMENT_ON	0x0
65 #define ADDRESS_INCREMENT_OFF	0x100
66 #define QUEUE_LENGTH_1		0x40
67 #define QUEUE_LENGTH_2		0x80
68 #define QUEUE_LENGTH_3		0xC0
69 #define QUEUE_LENGTH_4		0
70 #define CPU_TRANSFER_SIZE_32	0
71 #define CPU_TRANSFER_SIZE_16	0x10
72 #define CPU_TRANSFER_SIZE_8	0x20
73 #define READ_ENDIANNESS_ABCD	0
74 #define READ_ENDIANNESS_DCBA	0x4
75 #define READ_ENDIANNESS_BADC	0x8
76 #define READ_ENDIANNESS_CDAB	0xC
77 #define WRITE_ENDIANNESS_ABCD	0
78 #define WRITE_ENDIANNESS_DCBA	0x1
79 #define WRITE_ENDIANNESS_BADC	0x2
80 #define WRITE_ENDIANNESS_CDAB	0x3
81 
82 /* various bits in configuration register EBI_CTRL_SIG_ACTLV */
83 #define IORDY_ACTIVELEVEL_HIGH	(1 << 14)
84 #define ALE_ACTIVELEVEL_HIGH	(1 <<  8)
85 
86 /* bits in register EBI_SIG_LEVEL */
87 #define IORDY_LEVEL_MASK	1
88 
89 static inline void ebi_wait(void)
90 {
91 	while (reg_read(EBI_STATUS(EBI_BASE)) & EXT_CPU_ACCESS_ACTIVE)
92 		;	/* wait */
93 }
94 
95 #endif
96