1 /* 2 * Copyright (C) 2014 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <miiphy.h> 9 #include <asm/io.h> 10 #include <asm/arch/cpu.h> 11 #include <asm/arch/soc.h> 12 #include <linux/mbus.h> 13 14 #include "../drivers/ddr/marvell/axp/ddr3_hw_training.h" 15 #include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h" 16 17 DECLARE_GLOBAL_DATA_PTR; 18 19 /* Base addresses for the external device chip selects */ 20 #define DEV_CS0_BASE 0xe0000000 21 #define DEV_CS1_BASE 0xe1000000 22 #define DEV_CS2_BASE 0xe2000000 23 #define DEV_CS3_BASE 0xe3000000 24 25 /* DDR3 static configuration */ 26 MV_DRAM_MC_INIT ddr3_b0_maxbcm[MV_MAX_DDR3_STATIC_SIZE] = { 27 {0x00001400, 0x7301CC30}, /* DDR SDRAM Configuration Register */ 28 {0x00001404, 0x30000820}, /* Dunit Control Low Register */ 29 {0x00001408, 0x5515BAAB}, /* DDR SDRAM Timing (Low) Register */ 30 {0x0000140C, 0x38DA3F97}, /* DDR SDRAM Timing (High) Register */ 31 {0x00001410, 0x20100005}, /* DDR SDRAM Address Control Register */ 32 {0x00001414, 0x0000F3FF}, /* DDR SDRAM Open Pages Control Reg */ 33 {0x00001418, 0x00000e00}, /* DDR SDRAM Operation Register */ 34 {0x0000141C, 0x00000672}, /* DDR SDRAM Mode Register */ 35 {0x00001420, 0x00000004}, /* DDR SDRAM Extended Mode Register */ 36 {0x00001424, 0x0000F3FF}, /* Dunit Control High Register */ 37 {0x00001428, 0x0011A940}, /* Dunit Control High Register */ 38 {0x0000142C, 0x014C5134}, /* Dunit Control High Register */ 39 {0x0000147C, 0x0000D771}, 40 41 {0x00001494, 0x00010000}, /* DDR SDRAM ODT Control (Low) Reg */ 42 {0x0000149C, 0x00000001}, /* DDR Dunit ODT Control Register */ 43 {0x000014A0, 0x00000001}, 44 {0x000014A8, 0x00000101}, 45 46 /* Recommended Settings from Marvell for 4 x 16 bit devices: */ 47 {0x000014C0, 0x192424C9}, /* DRAM addr and Ctrl Driving Strenght*/ 48 {0x000014C4, 0xAAA24C9}, /* DRAM Data and DQS Driving Strenght */ 49 50 /* 51 * DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the 52 * training sequence 53 */ 54 {0x000200e8, 0x3FFF0E01}, 55 {0x00020184, 0x3FFFFFE0}, /* Close fast path Window to - 2G */ 56 57 {0x0001504, 0x3FFFFFE1}, /* CS0 Size */ 58 {0x000150C, 0x00000000}, /* CS1 Size */ 59 {0x0001514, 0x00000000}, /* CS2 Size */ 60 {0x000151C, 0x00000000}, /* CS3 Size */ 61 62 {0x0020220, 0x00000007}, /* Reserved */ 63 64 {0x00001538, 0x0000000B}, /* Read Data Sample Delays Register */ 65 {0x0000153C, 0x0000000B}, /* Read Data Ready Delay Register */ 66 67 {0x000015D0, 0x00000670}, /* MR0 */ 68 {0x000015D4, 0x00000044}, /* MR1 */ 69 {0x000015D8, 0x00000018}, /* MR2 */ 70 {0x000015DC, 0x00000000}, /* MR3 */ 71 {0x000015E0, 0x00000001}, 72 {0x000015E4, 0x00203c18}, /* ZQDS Configuration Register */ 73 {0x000015EC, 0xF800A225}, /* DDR PHY */ 74 75 {0x0, 0x0} 76 }; 77 78 MV_DRAM_MODES maxbcm_ddr_modes[MV_DDR3_MODES_NUMBER] = { 79 {"maxbcm_1600-800", 0xB, 0x5, 0x0, A0, ddr3_b0_maxbcm, NULL}, 80 }; 81 82 extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[]; 83 84 /* MAXBCM: SERDES 0-4 PCIE, Serdes 7 = SGMII 0, all others = unconnected */ 85 MV_BIN_SERDES_CFG maxbcm_serdes_cfg[] = { 86 { MV_PEX_ROOT_COMPLEX, 0x20011111, 0x00000000, 87 { PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_DISABLED, 88 PEX_BUS_DISABLED }, 89 0x1f, serdes_change_m_phy 90 } 91 }; 92 93 MV_DRAM_MODES *ddr3_get_static_ddr_mode(void) 94 { 95 /* Only one mode supported for this board */ 96 return &maxbcm_ddr_modes[0]; 97 } 98 99 MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode) 100 { 101 return &maxbcm_serdes_cfg[0]; 102 } 103 104 int board_early_init_f(void) 105 { 106 /* 107 * Don't configure MPP (pin multiplexing) and GPIO here, 108 * its already done in bin_hdr 109 */ 110 111 /* 112 * Setup some board specific mbus address windows 113 */ 114 mbus_dt_setup_win(&mbus_state, DEV_CS0_BASE, 16 << 20, 115 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS0); 116 mbus_dt_setup_win(&mbus_state, DEV_CS1_BASE, 16 << 20, 117 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS1); 118 mbus_dt_setup_win(&mbus_state, DEV_CS2_BASE, 16 << 20, 119 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS2); 120 mbus_dt_setup_win(&mbus_state, DEV_CS3_BASE, 16 << 20, 121 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS3); 122 123 return 0; 124 } 125 126 int board_init(void) 127 { 128 /* adress of boot parameters */ 129 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; 130 131 return 0; 132 } 133 134 int checkboard(void) 135 { 136 puts("Board: maxBCM\n"); 137 138 return 0; 139 } 140 141 #ifdef CONFIG_RESET_PHY_R 142 /* Configure and enable MV88E6185 switch */ 143 void reset_phy(void) 144 { 145 char *name = "neta0"; 146 147 if (miiphy_set_current_dev(name)) 148 return; 149 150 /* todo: fill this with the real setup / config code */ 151 152 printf("88E6185 Initialized on %s\n", name); 153 } 154 #endif /* CONFIG_RESET_PHY_R */ 155