1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2014 Stefan Roese <sr@denx.de> 4 */ 5 6 #include <common.h> 7 #include <miiphy.h> 8 #include <asm/io.h> 9 #include <asm/arch/cpu.h> 10 #include <asm/arch/soc.h> 11 #include <linux/mbus.h> 12 13 #include "../drivers/ddr/marvell/axp/ddr3_hw_training.h" 14 #include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h" 15 16 DECLARE_GLOBAL_DATA_PTR; 17 18 /* Base addresses for the external device chip selects */ 19 #define DEV_CS0_BASE 0xe0000000 20 #define DEV_CS1_BASE 0xe1000000 21 #define DEV_CS2_BASE 0xe2000000 22 #define DEV_CS3_BASE 0xe3000000 23 24 /* DDR3 static configuration */ 25 MV_DRAM_MC_INIT ddr3_b0_maxbcm[MV_MAX_DDR3_STATIC_SIZE] = { 26 {0x00001400, 0x7301CC30}, /* DDR SDRAM Configuration Register */ 27 {0x00001404, 0x30000820}, /* Dunit Control Low Register */ 28 {0x00001408, 0x5515BAAB}, /* DDR SDRAM Timing (Low) Register */ 29 {0x0000140C, 0x38DA3F97}, /* DDR SDRAM Timing (High) Register */ 30 {0x00001410, 0x20100005}, /* DDR SDRAM Address Control Register */ 31 {0x00001414, 0x0000F3FF}, /* DDR SDRAM Open Pages Control Reg */ 32 {0x00001418, 0x00000e00}, /* DDR SDRAM Operation Register */ 33 {0x0000141C, 0x00000672}, /* DDR SDRAM Mode Register */ 34 {0x00001420, 0x00000004}, /* DDR SDRAM Extended Mode Register */ 35 {0x00001424, 0x0000F3FF}, /* Dunit Control High Register */ 36 {0x00001428, 0x0011A940}, /* Dunit Control High Register */ 37 {0x0000142C, 0x014C5134}, /* Dunit Control High Register */ 38 {0x0000147C, 0x0000D771}, 39 40 {0x00001494, 0x00010000}, /* DDR SDRAM ODT Control (Low) Reg */ 41 {0x0000149C, 0x00000001}, /* DDR Dunit ODT Control Register */ 42 {0x000014A0, 0x00000001}, 43 {0x000014A8, 0x00000101}, 44 45 /* Recommended Settings from Marvell for 4 x 16 bit devices: */ 46 {0x000014C0, 0x192424C9}, /* DRAM addr and Ctrl Driving Strenght*/ 47 {0x000014C4, 0xAAA24C9}, /* DRAM Data and DQS Driving Strenght */ 48 49 /* 50 * DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the 51 * training sequence 52 */ 53 {0x000200e8, 0x3FFF0E01}, 54 {0x00020184, 0x3FFFFFE0}, /* Close fast path Window to - 2G */ 55 56 {0x0001504, 0x3FFFFFE1}, /* CS0 Size */ 57 {0x000150C, 0x00000000}, /* CS1 Size */ 58 {0x0001514, 0x00000000}, /* CS2 Size */ 59 {0x000151C, 0x00000000}, /* CS3 Size */ 60 61 {0x0020220, 0x00000007}, /* Reserved */ 62 63 {0x00001538, 0x0000000B}, /* Read Data Sample Delays Register */ 64 {0x0000153C, 0x0000000B}, /* Read Data Ready Delay Register */ 65 66 {0x000015D0, 0x00000670}, /* MR0 */ 67 {0x000015D4, 0x00000044}, /* MR1 */ 68 {0x000015D8, 0x00000018}, /* MR2 */ 69 {0x000015DC, 0x00000000}, /* MR3 */ 70 {0x000015E0, 0x00000001}, 71 {0x000015E4, 0x00203c18}, /* ZQDS Configuration Register */ 72 {0x000015EC, 0xF800A225}, /* DDR PHY */ 73 74 {0x0, 0x0} 75 }; 76 77 MV_DRAM_MODES maxbcm_ddr_modes[MV_DDR3_MODES_NUMBER] = { 78 {"maxbcm_1600-800", 0xB, 0x5, 0x0, A0, ddr3_b0_maxbcm, NULL}, 79 }; 80 81 extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[]; 82 83 /* MAXBCM: SERDES 0-4 PCIE, Serdes 7 = SGMII 0, all others = unconnected */ 84 MV_BIN_SERDES_CFG maxbcm_serdes_cfg[] = { 85 { MV_PEX_ROOT_COMPLEX, 0x20011111, 0x00000000, 86 { PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_DISABLED, 87 PEX_BUS_DISABLED }, 88 0x1f, serdes_change_m_phy 89 } 90 }; 91 92 MV_DRAM_MODES *ddr3_get_static_ddr_mode(void) 93 { 94 /* Only one mode supported for this board */ 95 return &maxbcm_ddr_modes[0]; 96 } 97 98 MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode) 99 { 100 return &maxbcm_serdes_cfg[0]; 101 } 102 103 int board_early_init_f(void) 104 { 105 /* 106 * Don't configure MPP (pin multiplexing) and GPIO here, 107 * its already done in bin_hdr 108 */ 109 110 /* 111 * Setup some board specific mbus address windows 112 */ 113 mbus_dt_setup_win(&mbus_state, DEV_CS0_BASE, 16 << 20, 114 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS0); 115 mbus_dt_setup_win(&mbus_state, DEV_CS1_BASE, 16 << 20, 116 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS1); 117 mbus_dt_setup_win(&mbus_state, DEV_CS2_BASE, 16 << 20, 118 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS2); 119 mbus_dt_setup_win(&mbus_state, DEV_CS3_BASE, 16 << 20, 120 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS3); 121 122 return 0; 123 } 124 125 int board_init(void) 126 { 127 /* adress of boot parameters */ 128 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; 129 130 return 0; 131 } 132 133 int checkboard(void) 134 { 135 puts("Board: maxBCM\n"); 136 137 return 0; 138 } 139 140 /* Configure and enable MV88E6185 switch */ 141 int board_phy_config(struct phy_device *phydev) 142 { 143 /* 144 * todo: 145 * Fill this with the real setup / config code. 146 * Please see board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c 147 * for details. 148 */ 149 printf("88E6185 Initialized\n"); 150 return 0; 151 } 152