1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2011 4 * Logic Product Development <www.logicpd.com> 5 * 6 * Author : 7 * Peter Barada <peter.barada@logicpd.com> 8 * 9 * Derived from Beagle Board and 3430 SDP code by 10 * Richard Woodruff <r-woodruff2@ti.com> 11 * Syed Mohammed Khasim <khasim@ti.com> 12 */ 13 #include <common.h> 14 #include <dm.h> 15 #include <ns16550.h> 16 #include <netdev.h> 17 #include <flash.h> 18 #include <nand.h> 19 #include <i2c.h> 20 #include <twl4030.h> 21 #include <asm/io.h> 22 #include <asm/arch/mmc_host_def.h> 23 #include <asm/arch/mux.h> 24 #include <asm/arch/mem.h> 25 #include <asm/arch/sys_proto.h> 26 #include <asm/gpio.h> 27 #include <asm/omap_mmc.h> 28 #include <asm/mach-types.h> 29 #include <linux/mtd/rawnand.h> 30 #include <asm/omap_musb.h> 31 #include <linux/errno.h> 32 #include <linux/usb/ch9.h> 33 #include <linux/usb/gadget.h> 34 #include <linux/usb/musb.h> 35 #include "omap3logic.h" 36 #ifdef CONFIG_USB_EHCI_HCD 37 #include <usb.h> 38 #include <asm/ehci-omap.h> 39 #endif 40 41 DECLARE_GLOBAL_DATA_PTR; 42 43 /* This is only needed until SPL gets OF support */ 44 #ifdef CONFIG_SPL_BUILD 45 static const struct ns16550_platdata omap3logic_serial = { 46 .base = OMAP34XX_UART1, 47 .reg_shift = 2, 48 .clock = V_NS16550_CLK, 49 .fcr = UART_FCR_DEFVAL, 50 }; 51 52 U_BOOT_DEVICE(omap3logic_uart) = { 53 "ns16550_serial", 54 &omap3logic_serial 55 }; 56 57 static const struct omap_hsmmc_plat omap3_logic_mmc0_platdata = { 58 .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE, 59 .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT, 60 .cfg.f_min = 400000, 61 .cfg.f_max = 52000000, 62 .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195, 63 .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, 64 }; 65 66 U_BOOT_DEVICE(am335x_mmc0) = { 67 .name = "omap_hsmmc", 68 .platdata = &omap3_logic_mmc0_platdata, 69 }; 70 71 #endif 72 73 /* 74 * two dimensional array of strucures containining board name and Linux 75 * machine IDs; row it selected based on CPU column is slected based 76 * on hsusb0_data5 pin having a pulldown resistor 77 */ 78 static struct board_id { 79 char *name; 80 int machine_id; 81 char *fdtfile; 82 } boards[2][2] = { 83 { 84 { 85 .name = "OMAP35xx SOM LV", 86 .machine_id = MACH_TYPE_OMAP3530_LV_SOM, 87 .fdtfile = "logicpd-som-lv-35xx-devkit.dtb", 88 }, 89 { 90 .name = "OMAP35xx Torpedo", 91 .machine_id = MACH_TYPE_OMAP3_TORPEDO, 92 .fdtfile = "logicpd-torpedo-35xx-devkit.dtb", 93 }, 94 }, 95 { 96 { 97 .name = "DM37xx SOM LV", 98 .fdtfile = "logicpd-som-lv-37xx-devkit.dtb", 99 }, 100 { 101 .name = "DM37xx Torpedo", 102 .fdtfile = "logicpd-torpedo-37xx-devkit.dtb", 103 }, 104 }, 105 }; 106 107 #ifdef CONFIG_SPL_OS_BOOT 108 int spl_start_uboot(void) 109 { 110 /* break into full u-boot on 'c' */ 111 return serial_tstc() && serial_getc() == 'c'; 112 } 113 #endif 114 115 #if defined(CONFIG_SPL_BUILD) 116 /* 117 * Routine: get_board_mem_timings 118 * Description: If we use SPL then there is no x-loader nor config header 119 * so we have to setup the DDR timings ourself on the first bank. This 120 * provides the timing values back to the function that configures 121 * the memory. 122 */ 123 void get_board_mem_timings(struct board_sdrc_timings *timings) 124 { 125 timings->mr = MICRON_V_MR_165; 126 /* 256MB DDR */ 127 timings->mcfg = MICRON_V_MCFG_200(256 << 20); 128 timings->ctrla = MICRON_V_ACTIMA_200; 129 timings->ctrlb = MICRON_V_ACTIMB_200; 130 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 131 } 132 133 #define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE + 0x7c) 134 #define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE + 0x84) 135 #define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE + 0x80) 136 137 void spl_board_prepare_for_linux(void) 138 { 139 /* The Micron NAND starts locked which 140 * prohibits mounting the NAND as RW 141 * The following commands are what unlocks 142 * the NAND to become RW Falcon Mode does not 143 * have as many smarts as U-Boot, but Logic PD 144 * only makes NAND with 512MB so these hard coded 145 * values should work for all current models 146 */ 147 148 writeb(0x70, GPMC_NAND_COMMAND_0); 149 writeb(-1, GPMC_NAND_DATA_0); 150 writeb(0x7a, GPMC_NAND_COMMAND_0); 151 writeb(0x00, GPMC_NAND_ADDRESS_0); 152 writeb(0x00, GPMC_NAND_ADDRESS_0); 153 writeb(0x00, GPMC_NAND_ADDRESS_0); 154 writeb(-1, GPMC_NAND_COMMAND_0); 155 156 /* Begin address 0 */ 157 writeb(NAND_CMD_UNLOCK1, 0x6e00007c); 158 writeb(0x00, GPMC_NAND_ADDRESS_0); 159 writeb(0x00, GPMC_NAND_ADDRESS_0); 160 writeb(0x00, GPMC_NAND_ADDRESS_0); 161 writeb(-1, GPMC_NAND_DATA_0); 162 163 /* Ending address at the end of Flash */ 164 writeb(NAND_CMD_UNLOCK2, GPMC_NAND_COMMAND_0); 165 writeb(0xc0, GPMC_NAND_ADDRESS_0); 166 writeb(0xff, GPMC_NAND_ADDRESS_0); 167 writeb(0x03, GPMC_NAND_ADDRESS_0); 168 writeb(-1, GPMC_NAND_DATA_0); 169 writeb(0x79, GPMC_NAND_COMMAND_0); 170 writeb(-1, GPMC_NAND_DATA_0); 171 writeb(-1, GPMC_NAND_DATA_0); 172 } 173 #endif 174 175 #ifdef CONFIG_USB_MUSB_OMAP2PLUS 176 static struct musb_hdrc_config musb_config = { 177 .multipoint = 1, 178 .dyn_fifo = 1, 179 .num_eps = 16, 180 .ram_bits = 12, 181 }; 182 183 static struct omap_musb_board_data musb_board_data = { 184 .interface_type = MUSB_INTERFACE_ULPI, 185 }; 186 187 static struct musb_hdrc_platform_data musb_plat = { 188 #if defined(CONFIG_USB_MUSB_HOST) 189 .mode = MUSB_HOST, 190 #elif defined(CONFIG_USB_MUSB_GADGET) 191 .mode = MUSB_PERIPHERAL, 192 #else 193 #error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET" 194 #endif 195 .config = &musb_config, 196 .power = 100, 197 .platform_ops = &omap2430_ops, 198 .board_data = &musb_board_data, 199 }; 200 #endif 201 202 #if defined(CONFIG_USB_EHCI_HCD) && !defined(CONFIG_SPL_BUILD) 203 /* Call usb_stop() before starting the kernel */ 204 void show_boot_progress(int val) 205 { 206 if (val == BOOTSTAGE_ID_RUN_OS) 207 usb_stop(); 208 } 209 210 static struct omap_usbhs_board_data usbhs_bdata = { 211 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, 212 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, 213 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED 214 }; 215 216 int ehci_hcd_init(int index, enum usb_init_type init, 217 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 218 { 219 return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); 220 } 221 222 int ehci_hcd_stop(int index) 223 { 224 return omap_ehci_hcd_stop(); 225 } 226 227 #endif /* CONFIG_USB_EHCI_HCD */ 228 229 230 /* 231 * Routine: misc_init_r 232 * Description: Configure board specific parts 233 */ 234 int misc_init_r(void) 235 { 236 twl4030_power_init(); 237 omap_die_id_display(); 238 239 #ifdef CONFIG_USB_MUSB_OMAP2PLUS 240 musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE); 241 #endif 242 243 return 0; 244 } 245 246 /* 247 * BOARD_ID_GPIO - GPIO of pin with optional pulldown resistor on SOM LV 248 */ 249 #define BOARD_ID_GPIO 189 /* hsusb0_data5 pin */ 250 251 /* 252 * Routine: board_init 253 * Description: Early hardware init. 254 */ 255 int board_init(void) 256 { 257 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ 258 259 /* boot param addr */ 260 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 261 262 return 0; 263 } 264 265 #ifdef CONFIG_BOARD_LATE_INIT 266 267 static void unlock_nand(void) 268 { 269 int dev = nand_curr_device; 270 struct mtd_info *mtd; 271 272 mtd = get_nand_dev_by_index(dev); 273 nand_unlock(mtd, 0, mtd->size, 0); 274 } 275 276 int board_late_init(void) 277 { 278 struct board_id *board; 279 unsigned int val; 280 281 /* 282 * To identify between a SOM LV and Torpedo module, 283 * a pulldown resistor is on hsusb0_data5 for the SOM LV module. 284 * Drive the pin (and let it soak), then read it back. 285 * If the pin is still high its a Torpedo. If low its a SOM LV 286 */ 287 288 /* Mux hsusb0_data5 as a GPIO */ 289 MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M4)); 290 291 if (gpio_request(BOARD_ID_GPIO, "husb0_data5.gpio_189") == 0) { 292 293 /* 294 * Drive BOARD_ID_GPIO - the pulldown resistor on the SOM LV 295 * will drain the voltage. 296 */ 297 gpio_direction_output(BOARD_ID_GPIO, 0); 298 gpio_set_value(BOARD_ID_GPIO, 1); 299 300 /* Let it soak for a bit */ 301 sdelay(0x100); 302 303 /* 304 * Read state of BOARD_ID_GPIO as an input and if its set. 305 * If so the board is a Torpedo 306 */ 307 gpio_direction_input(BOARD_ID_GPIO); 308 val = gpio_get_value(BOARD_ID_GPIO); 309 gpio_free(BOARD_ID_GPIO); 310 311 board = &boards[!!(get_cpu_family() == CPU_OMAP36XX)][!!val]; 312 printf("Board: %s\n", board->name); 313 314 /* Set the machine_id passed to Linux */ 315 if (board->machine_id) 316 gd->bd->bi_arch_number = board->machine_id; 317 318 /* If the user has not set fdtimage, set the default */ 319 if (!env_get("fdtimage")) 320 env_set("fdtimage", board->fdtfile); 321 } 322 323 /* restore hsusb0_data5 pin as hsusb0_data5 */ 324 MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); 325 326 #ifdef CONFIG_CMD_NAND_LOCK_UNLOCK 327 unlock_nand(); 328 #endif 329 return 0; 330 } 331 #endif 332 333 #if defined(CONFIG_MMC) 334 int board_mmc_init(bd_t *bis) 335 { 336 return omap_mmc_init(0, 0, 0, -1, -1); 337 } 338 #endif 339 340 #if defined(CONFIG_MMC) 341 void board_mmc_power_init(void) 342 { 343 twl4030_power_mmc_init(0); 344 } 345 #endif 346 347 #ifdef CONFIG_SMC911X 348 /* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */ 349 static const u32 gpmc_lan92xx_config[] = { 350 NET_LAN92XX_GPMC_CONFIG1, 351 NET_LAN92XX_GPMC_CONFIG2, 352 NET_LAN92XX_GPMC_CONFIG3, 353 NET_LAN92XX_GPMC_CONFIG4, 354 NET_LAN92XX_GPMC_CONFIG5, 355 NET_LAN92XX_GPMC_CONFIG6, 356 }; 357 358 int board_eth_init(bd_t *bis) 359 { 360 enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1], 361 CONFIG_SMC911X_BASE, GPMC_SIZE_16M); 362 363 return smc911x_initialize(0, CONFIG_SMC911X_BASE); 364 } 365 #endif 366 367 368