1 /*
2  * (C) Copyright 2011
3  * Logic Product Development <www.logicpd.com>
4  *
5  * Author :
6  *	Peter Barada <peter.barada@logicpd.com>
7  *
8  * Derived from Beagle Board and 3430 SDP code by
9  *	Richard Woodruff <r-woodruff2@ti.com>
10  *	Syed Mohammed Khasim <khasim@ti.com>
11  *
12  * SPDX-License-Identifier:	GPL-2.0+
13  */
14 #include <common.h>
15 #include <dm.h>
16 #include <ns16550.h>
17 #include <netdev.h>
18 #include <flash.h>
19 #include <nand.h>
20 #include <i2c.h>
21 #include <twl4030.h>
22 #include <asm/io.h>
23 #include <asm/arch/mmc_host_def.h>
24 #include <asm/arch/mux.h>
25 #include <asm/arch/mem.h>
26 #include <asm/arch/sys_proto.h>
27 #include <asm/gpio.h>
28 #include <asm/mach-types.h>
29 #include "omap3logic.h"
30 
31 DECLARE_GLOBAL_DATA_PTR;
32 
33 /*
34  * two dimensional array of strucures containining board name and Linux
35  * machine IDs; row it selected based on CPU column is slected based
36  * on hsusb0_data5 pin having a pulldown resistor
37  */
38 
39 static const struct ns16550_platdata omap3logic_serial = {
40 	OMAP34XX_UART1,
41 	2,
42 	V_NS16550_CLK
43 };
44 
45 U_BOOT_DEVICE(omap3logic_uart) = {
46 	"serial_omap",
47 	&omap3logic_serial
48 };
49 
50 static struct board_id {
51 	char *name;
52 	int machine_id;
53 } boards[2][2] = {
54 	{
55 		{
56 			.name		= "OMAP35xx SOM LV",
57 			.machine_id	= MACH_TYPE_OMAP3530_LV_SOM,
58 		},
59 		{
60 			.name		= "OMAP35xx Torpedo",
61 			.machine_id	= MACH_TYPE_OMAP3_TORPEDO,
62 		},
63 	},
64 	{
65 		{
66 			.name		= "DM37xx SOM LV",
67 			.machine_id	= MACH_TYPE_DM3730_SOM_LV,
68 		},
69 		{
70 			.name		= "DM37xx Torpedo",
71 			.machine_id	= MACH_TYPE_DM3730_TORPEDO,
72 		},
73 	},
74 };
75 
76 /*
77  * BOARD_ID_GPIO - GPIO of pin with optional pulldown resistor on SOM LV
78  */
79 #define BOARD_ID_GPIO	189 /* hsusb0_data5 pin */
80 
81 /*
82  * Routine: board_init
83  * Description: Early hardware init.
84  */
85 int board_init(void)
86 {
87 	struct board_id *board;
88 	unsigned int val;
89 
90 	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
91 
92 	/* boot param addr */
93 	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
94 
95 	/*
96 	 * To identify between a SOM LV and Torpedo module,
97 	 * a pulldown resistor is on hsusb0_data5 for the SOM LV module.
98 	 * Drive the pin (and let it soak), then read it back.
99 	 * If the pin is still high its a Torpedo.  If low its a SOM LV
100 	 */
101 
102 	/* Mux hsusb0_data5 as a GPIO */
103 	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M4));
104 
105 	if (gpio_request(BOARD_ID_GPIO, "husb0_data5.gpio_189") == 0) {
106 
107 		/*
108 		 * Drive BOARD_ID_GPIO - the pulldown resistor on the SOM LV
109 		 * will drain the voltage.
110 		 */
111 		gpio_direction_output(BOARD_ID_GPIO, 0);
112 		gpio_set_value(BOARD_ID_GPIO, 1);
113 
114 		/* Let it soak for a bit */
115 		sdelay(0x100);
116 
117 		/*
118 		 * Read state of BOARD_ID_GPIO as an input and if its set.
119 		 * If so the board is a Torpedo
120 		 */
121 		gpio_direction_input(BOARD_ID_GPIO);
122 		val = gpio_get_value(BOARD_ID_GPIO);
123 		gpio_free(BOARD_ID_GPIO);
124 
125 		board = &boards[!!(get_cpu_family() == CPU_OMAP36XX)][!!val];
126 		printf("Board: %s\n", board->name);
127 
128 		/* Set the machine_id passed to Linux */
129 		gd->bd->bi_arch_number = board->machine_id;
130 	}
131 
132 	/* restore hsusb0_data5 pin as hsusb0_data5 */
133 	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0));
134 
135 	return 0;
136 }
137 
138 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
139 int board_mmc_init(bd_t *bis)
140 {
141 	return omap_mmc_init(0, 0, 0, -1, -1);
142 }
143 #endif
144 
145 #if defined(CONFIG_GENERIC_MMC)
146 void board_mmc_power_init(void)
147 {
148 	twl4030_power_mmc_init(0);
149 }
150 #endif
151 
152 #ifdef CONFIG_SMC911X
153 /* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
154 static const u32 gpmc_lan92xx_config[] = {
155 	NET_LAN92XX_GPMC_CONFIG1,
156 	NET_LAN92XX_GPMC_CONFIG2,
157 	NET_LAN92XX_GPMC_CONFIG3,
158 	NET_LAN92XX_GPMC_CONFIG4,
159 	NET_LAN92XX_GPMC_CONFIG5,
160 	NET_LAN92XX_GPMC_CONFIG6,
161 };
162 
163 int board_eth_init(bd_t *bis)
164 {
165 	enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1],
166 			CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
167 
168 	return smc911x_initialize(0, CONFIG_SMC911X_BASE);
169 }
170 #endif
171 
172 /*
173  * IEN  - Input Enable
174  * IDIS - Input Disable
175  * PTD  - Pull type Down
176  * PTU  - Pull type Up
177  * DIS  - Pull type selection is inactive
178  * EN   - Pull type selection is active
179  * M0   - Mode 0
180  * The commented string gives the final mux configuration for that pin
181  */
182 
183 /*
184  * Routine: set_muxconf_regs
185  * Description: Setting up the configuration Mux registers specific to the
186  *		hardware. Many pins need to be moved from protect to primary
187  *		mode.
188  */
189 void set_muxconf_regs(void)
190 {
191 	/*GPMC*/
192 	MUX_VAL(CP(GPMC_A1),		(IDIS | PTU | EN  | M0));
193 	MUX_VAL(CP(GPMC_A2),		(IDIS | PTU | EN  | M0));
194 	MUX_VAL(CP(GPMC_A3),		(IDIS | PTU | EN  | M0));
195 	MUX_VAL(CP(GPMC_A4),		(IDIS | PTU | EN  | M0));
196 	MUX_VAL(CP(GPMC_A5),		(IDIS | PTU | EN  | M0));
197 	MUX_VAL(CP(GPMC_A6),		(IDIS | PTU | EN  | M0));
198 	MUX_VAL(CP(GPMC_A7),		(IDIS | PTU | EN  | M0));
199 	MUX_VAL(CP(GPMC_A8),		(IDIS | PTU | EN  | M0));
200 	MUX_VAL(CP(GPMC_A9),		(IDIS | PTU | EN  | M0));
201 	MUX_VAL(CP(GPMC_A10),		(IDIS | PTU | EN  | M0));
202 	MUX_VAL(CP(GPMC_D0),		(IEN  | PTU | EN  | M0));
203 	MUX_VAL(CP(GPMC_D1),		(IEN  | PTU | EN  | M0));
204 	MUX_VAL(CP(GPMC_D2),		(IEN  | PTU | EN  | M0));
205 	MUX_VAL(CP(GPMC_D3),		(IEN  | PTU | EN  | M0));
206 	MUX_VAL(CP(GPMC_D4),		(IEN  | PTU | EN  | M0));
207 	MUX_VAL(CP(GPMC_D5),		(IEN  | PTU | EN  | M0));
208 	MUX_VAL(CP(GPMC_D6),		(IEN  | PTU | EN  | M0));
209 	MUX_VAL(CP(GPMC_D7),		(IEN  | PTU | EN  | M0));
210 	MUX_VAL(CP(GPMC_D8),		(IEN  | PTU | EN  | M0));
211 	MUX_VAL(CP(GPMC_D9),		(IEN  | PTU | EN  | M0));
212 	MUX_VAL(CP(GPMC_D10),		(IEN  | PTU | EN  | M0));
213 	MUX_VAL(CP(GPMC_D11),		(IEN  | PTU | EN  | M0));
214 	MUX_VAL(CP(GPMC_D12),		(IEN  | PTU | EN  | M0));
215 	MUX_VAL(CP(GPMC_D13),		(IEN  | PTU | EN  | M0));
216 	MUX_VAL(CP(GPMC_D14),		(IEN  | PTU | EN  | M0));
217 	MUX_VAL(CP(GPMC_D15),		(IEN  | PTU | EN  | M0));
218 	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0));
219 	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0));
220 	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M0));
221 	MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTD | DIS | M0));
222 	MUX_VAL(CP(GPMC_NCS5),          (IDIS | PTU | DIS | M4));
223 	MUX_VAL(CP(GPMC_NCS7),		(IDIS | PTD | DIS | M1)); /*GPMC_IO_DIR*/
224 	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTU | EN  | M0));
225 	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0));
226 
227 	/*Expansion card  */
228 	MUX_VAL(CP(MMC1_CLK),		(IDIS | PTU | EN  | M0));
229 	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | EN  | M0));
230 	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | EN  | M0));
231 	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | EN  | M0));
232 	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | EN  | M0));
233 	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | EN  | M0));
234 
235 	/* Serial Console */
236 	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0));
237 	MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M0));
238 	MUX_VAL(CP(UART1_CTS),		(IEN  | PTU | DIS | M0));
239 	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0));
240 
241 	/* I2C */
242 	MUX_VAL(CP(I2C2_SCL),		(IEN  | PTU | EN  | M0));
243 	MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M0));
244 	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0));
245 	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0));
246 
247 	MUX_VAL(CP(HDQ_SIO),		(IEN  | PTU | EN  | M0));
248 
249 	/*Control and debug */
250 	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0));
251 	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0));
252 	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M0));
253 	MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M0));
254 	MUX_VAL(CP(JTAG_NTRST),		(IEN  | PTD | DIS | M0));
255 	MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTU | EN  | M0));
256 }
257