1 /* 2 * (C) Copyright 2011 3 * Logic Product Development <www.logicpd.com> 4 * 5 * Author : 6 * Peter Barada <peter.barada@logicpd.com> 7 * 8 * Derived from Beagle Board and 3430 SDP code by 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * Syed Mohammed Khasim <khasim@ti.com> 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 #include <common.h> 15 #include <dm.h> 16 #include <ns16550.h> 17 #include <netdev.h> 18 #include <flash.h> 19 #include <nand.h> 20 #include <i2c.h> 21 #include <twl4030.h> 22 #include <asm/io.h> 23 #include <asm/arch/mmc_host_def.h> 24 #include <asm/arch/mux.h> 25 #include <asm/arch/mem.h> 26 #include <asm/arch/sys_proto.h> 27 #include <asm/gpio.h> 28 #include <asm/mach-types.h> 29 #include <linux/mtd/rawnand.h> 30 #include <asm/omap_musb.h> 31 #include <linux/errno.h> 32 #include <linux/usb/ch9.h> 33 #include <linux/usb/gadget.h> 34 #include <linux/usb/musb.h> 35 #include "omap3logic.h" 36 #ifdef CONFIG_USB_EHCI_HCD 37 #include <usb.h> 38 #include <asm/ehci-omap.h> 39 #endif 40 41 DECLARE_GLOBAL_DATA_PTR; 42 43 /* 44 * two dimensional array of strucures containining board name and Linux 45 * machine IDs; row it selected based on CPU column is slected based 46 * on hsusb0_data5 pin having a pulldown resistor 47 */ 48 static struct board_id { 49 char *name; 50 int machine_id; 51 char *fdtfile; 52 } boards[2][2] = { 53 { 54 { 55 .name = "OMAP35xx SOM LV", 56 .machine_id = MACH_TYPE_OMAP3530_LV_SOM, 57 .fdtfile = "logicpd-som-lv-35xx-devkit.dtb", 58 }, 59 { 60 .name = "OMAP35xx Torpedo", 61 .machine_id = MACH_TYPE_OMAP3_TORPEDO, 62 .fdtfile = "logicpd-torpedo-35xx-devkit.dtb", 63 }, 64 }, 65 { 66 { 67 .name = "DM37xx SOM LV", 68 .fdtfile = "logicpd-som-lv-37xx-devkit.dtb", 69 }, 70 { 71 .name = "DM37xx Torpedo", 72 .fdtfile = "logicpd-torpedo-37xx-devkit.dtb", 73 }, 74 }, 75 }; 76 77 #ifdef CONFIG_SPL_OS_BOOT 78 int spl_start_uboot(void) 79 { 80 /* break into full u-boot on 'c' */ 81 return serial_tstc() && serial_getc() == 'c'; 82 } 83 #endif 84 85 #if defined(CONFIG_SPL_BUILD) 86 /* 87 * Routine: get_board_mem_timings 88 * Description: If we use SPL then there is no x-loader nor config header 89 * so we have to setup the DDR timings ourself on the first bank. This 90 * provides the timing values back to the function that configures 91 * the memory. 92 */ 93 void get_board_mem_timings(struct board_sdrc_timings *timings) 94 { 95 timings->mr = MICRON_V_MR_165; 96 /* 256MB DDR */ 97 timings->mcfg = MICRON_V_MCFG_200(256 << 20); 98 timings->ctrla = MICRON_V_ACTIMA_200; 99 timings->ctrlb = MICRON_V_ACTIMB_200; 100 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 101 } 102 103 #define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE + 0x7c) 104 #define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE + 0x84) 105 #define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE + 0x80) 106 107 void spl_board_prepare_for_linux(void) 108 { 109 /* The Micron NAND starts locked which 110 * prohibits mounting the NAND as RW 111 * The following commands are what unlocks 112 * the NAND to become RW Falcon Mode does not 113 * have as many smarts as U-Boot, but Logic PD 114 * only makes NAND with 512MB so these hard coded 115 * values should work for all current models 116 */ 117 118 writeb(0x70, GPMC_NAND_COMMAND_0); 119 writeb(-1, GPMC_NAND_DATA_0); 120 writeb(0x7a, GPMC_NAND_COMMAND_0); 121 writeb(0x00, GPMC_NAND_ADDRESS_0); 122 writeb(0x00, GPMC_NAND_ADDRESS_0); 123 writeb(0x00, GPMC_NAND_ADDRESS_0); 124 writeb(-1, GPMC_NAND_COMMAND_0); 125 126 /* Begin address 0 */ 127 writeb(NAND_CMD_UNLOCK1, 0x6e00007c); 128 writeb(0x00, GPMC_NAND_ADDRESS_0); 129 writeb(0x00, GPMC_NAND_ADDRESS_0); 130 writeb(0x00, GPMC_NAND_ADDRESS_0); 131 writeb(-1, GPMC_NAND_DATA_0); 132 133 /* Ending address at the end of Flash */ 134 writeb(NAND_CMD_UNLOCK2, GPMC_NAND_COMMAND_0); 135 writeb(0xc0, GPMC_NAND_ADDRESS_0); 136 writeb(0xff, GPMC_NAND_ADDRESS_0); 137 writeb(0x03, GPMC_NAND_ADDRESS_0); 138 writeb(-1, GPMC_NAND_DATA_0); 139 writeb(0x79, GPMC_NAND_COMMAND_0); 140 writeb(-1, GPMC_NAND_DATA_0); 141 writeb(-1, GPMC_NAND_DATA_0); 142 } 143 #endif 144 145 #ifdef CONFIG_USB_MUSB_OMAP2PLUS 146 static struct musb_hdrc_config musb_config = { 147 .multipoint = 1, 148 .dyn_fifo = 1, 149 .num_eps = 16, 150 .ram_bits = 12, 151 }; 152 153 static struct omap_musb_board_data musb_board_data = { 154 .interface_type = MUSB_INTERFACE_ULPI, 155 }; 156 157 static struct musb_hdrc_platform_data musb_plat = { 158 #if defined(CONFIG_USB_MUSB_HOST) 159 .mode = MUSB_HOST, 160 #elif defined(CONFIG_USB_MUSB_GADGET) 161 .mode = MUSB_PERIPHERAL, 162 #else 163 #error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET" 164 #endif 165 .config = &musb_config, 166 .power = 100, 167 .platform_ops = &omap2430_ops, 168 .board_data = &musb_board_data, 169 }; 170 #endif 171 172 #if defined(CONFIG_USB_EHCI_HCD) && !defined(CONFIG_SPL_BUILD) 173 /* Call usb_stop() before starting the kernel */ 174 void show_boot_progress(int val) 175 { 176 if (val == BOOTSTAGE_ID_RUN_OS) 177 usb_stop(); 178 } 179 180 static struct omap_usbhs_board_data usbhs_bdata = { 181 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, 182 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, 183 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED 184 }; 185 186 int ehci_hcd_init(int index, enum usb_init_type init, 187 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 188 { 189 return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); 190 } 191 192 int ehci_hcd_stop(int index) 193 { 194 return omap_ehci_hcd_stop(); 195 } 196 197 #endif /* CONFIG_USB_EHCI_HCD */ 198 199 200 /* 201 * Routine: misc_init_r 202 * Description: Configure board specific parts 203 */ 204 int misc_init_r(void) 205 { 206 twl4030_power_init(); 207 omap_die_id_display(); 208 209 #ifdef CONFIG_USB_MUSB_OMAP2PLUS 210 musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE); 211 #endif 212 213 return 0; 214 } 215 216 /* 217 * BOARD_ID_GPIO - GPIO of pin with optional pulldown resistor on SOM LV 218 */ 219 #define BOARD_ID_GPIO 189 /* hsusb0_data5 pin */ 220 221 /* 222 * Routine: board_init 223 * Description: Early hardware init. 224 */ 225 int board_init(void) 226 { 227 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ 228 229 /* boot param addr */ 230 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 231 232 return 0; 233 } 234 235 #ifdef CONFIG_BOARD_LATE_INIT 236 237 static void unlock_nand(void) 238 { 239 int dev = nand_curr_device; 240 struct mtd_info *mtd; 241 242 mtd = get_nand_dev_by_index(dev); 243 nand_unlock(mtd, 0, mtd->size, 0); 244 } 245 246 int board_late_init(void) 247 { 248 struct board_id *board; 249 unsigned int val; 250 251 /* 252 * To identify between a SOM LV and Torpedo module, 253 * a pulldown resistor is on hsusb0_data5 for the SOM LV module. 254 * Drive the pin (and let it soak), then read it back. 255 * If the pin is still high its a Torpedo. If low its a SOM LV 256 */ 257 258 /* Mux hsusb0_data5 as a GPIO */ 259 MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M4)); 260 261 if (gpio_request(BOARD_ID_GPIO, "husb0_data5.gpio_189") == 0) { 262 263 /* 264 * Drive BOARD_ID_GPIO - the pulldown resistor on the SOM LV 265 * will drain the voltage. 266 */ 267 gpio_direction_output(BOARD_ID_GPIO, 0); 268 gpio_set_value(BOARD_ID_GPIO, 1); 269 270 /* Let it soak for a bit */ 271 sdelay(0x100); 272 273 /* 274 * Read state of BOARD_ID_GPIO as an input and if its set. 275 * If so the board is a Torpedo 276 */ 277 gpio_direction_input(BOARD_ID_GPIO); 278 val = gpio_get_value(BOARD_ID_GPIO); 279 gpio_free(BOARD_ID_GPIO); 280 281 board = &boards[!!(get_cpu_family() == CPU_OMAP36XX)][!!val]; 282 printf("Board: %s\n", board->name); 283 284 /* Set the machine_id passed to Linux */ 285 if (board->machine_id) 286 gd->bd->bi_arch_number = board->machine_id; 287 288 /* If the user has not set fdtimage, set the default */ 289 if (!env_get("fdtimage")) 290 env_set("fdtimage", board->fdtfile); 291 } 292 293 /* restore hsusb0_data5 pin as hsusb0_data5 */ 294 MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); 295 296 #ifdef CONFIG_CMD_NAND_LOCK_UNLOCK 297 unlock_nand(); 298 #endif 299 return 0; 300 } 301 #endif 302 303 #if defined(CONFIG_MMC) 304 int board_mmc_init(bd_t *bis) 305 { 306 return omap_mmc_init(0, 0, 0, -1, -1); 307 } 308 #endif 309 310 #if defined(CONFIG_MMC) 311 void board_mmc_power_init(void) 312 { 313 twl4030_power_mmc_init(0); 314 } 315 #endif 316 317 #ifdef CONFIG_SMC911X 318 /* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */ 319 static const u32 gpmc_lan92xx_config[] = { 320 NET_LAN92XX_GPMC_CONFIG1, 321 NET_LAN92XX_GPMC_CONFIG2, 322 NET_LAN92XX_GPMC_CONFIG3, 323 NET_LAN92XX_GPMC_CONFIG4, 324 NET_LAN92XX_GPMC_CONFIG5, 325 NET_LAN92XX_GPMC_CONFIG6, 326 }; 327 328 int board_eth_init(bd_t *bis) 329 { 330 enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1], 331 CONFIG_SMC911X_BASE, GPMC_SIZE_16M); 332 333 return smc911x_initialize(0, CONFIG_SMC911X_BASE); 334 } 335 #endif 336 337 338