1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2011 4 * Logic Product Development <www.logicpd.com> 5 * 6 * Author : 7 * Peter Barada <peter.barada@logicpd.com> 8 * 9 * Derived from Beagle Board and 3430 SDP code by 10 * Richard Woodruff <r-woodruff2@ti.com> 11 * Syed Mohammed Khasim <khasim@ti.com> 12 */ 13 #include <common.h> 14 #include <dm.h> 15 #include <ns16550.h> 16 #include <netdev.h> 17 #include <flash.h> 18 #include <nand.h> 19 #include <i2c.h> 20 #include <twl4030.h> 21 #include <asm/io.h> 22 #include <asm/arch/mmc_host_def.h> 23 #include <asm/arch/mux.h> 24 #include <asm/arch/mem.h> 25 #include <asm/arch/sys_proto.h> 26 #include <asm/gpio.h> 27 #include <asm/omap_mmc.h> 28 #include <asm/mach-types.h> 29 #include <linux/mtd/rawnand.h> 30 #include <asm/omap_musb.h> 31 #include <linux/errno.h> 32 #include <linux/usb/ch9.h> 33 #include <linux/usb/gadget.h> 34 #include <linux/usb/musb.h> 35 #include "omap3logic.h" 36 #ifdef CONFIG_USB_EHCI_HCD 37 #include <usb.h> 38 #include <asm/ehci-omap.h> 39 #endif 40 41 DECLARE_GLOBAL_DATA_PTR; 42 43 /* This is only needed until SPL gets OF support */ 44 #ifdef CONFIG_SPL_BUILD 45 static const struct ns16550_platdata omap3logic_serial = { 46 .base = OMAP34XX_UART1, 47 .reg_shift = 2, 48 .clock = V_NS16550_CLK, 49 .fcr = UART_FCR_DEFVAL, 50 }; 51 52 U_BOOT_DEVICE(omap3logic_uart) = { 53 "ns16550_serial", 54 &omap3logic_serial 55 }; 56 57 static const struct omap_hsmmc_plat omap3_logic_mmc0_platdata = { 58 .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE, 59 .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT, 60 .cfg.f_min = 400000, 61 .cfg.f_max = 52000000, 62 .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195, 63 .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, 64 }; 65 66 U_BOOT_DEVICE(am335x_mmc0) = { 67 .name = "omap_hsmmc", 68 .platdata = &omap3_logic_mmc0_platdata, 69 }; 70 71 #endif 72 73 #ifdef CONFIG_SPL_OS_BOOT 74 int spl_start_uboot(void) 75 { 76 /* break into full u-boot on 'c' */ 77 return serial_tstc() && serial_getc() == 'c'; 78 } 79 #endif 80 81 #if defined(CONFIG_SPL_BUILD) 82 /* 83 * Routine: get_board_mem_timings 84 * Description: If we use SPL then there is no x-loader nor config header 85 * so we have to setup the DDR timings ourself on the first bank. This 86 * provides the timing values back to the function that configures 87 * the memory. 88 */ 89 void get_board_mem_timings(struct board_sdrc_timings *timings) 90 { 91 timings->mr = MICRON_V_MR_165; 92 /* 256MB DDR */ 93 timings->mcfg = MICRON_V_MCFG_200(256 << 20); 94 timings->ctrla = MICRON_V_ACTIMA_200; 95 timings->ctrlb = MICRON_V_ACTIMB_200; 96 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 97 } 98 99 #define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE + 0x7c) 100 #define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE + 0x84) 101 #define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE + 0x80) 102 103 void spl_board_prepare_for_linux(void) 104 { 105 /* The Micron NAND starts locked which 106 * prohibits mounting the NAND as RW 107 * The following commands are what unlocks 108 * the NAND to become RW Falcon Mode does not 109 * have as many smarts as U-Boot, but Logic PD 110 * only makes NAND with 512MB so these hard coded 111 * values should work for all current models 112 */ 113 114 writeb(0x70, GPMC_NAND_COMMAND_0); 115 writeb(-1, GPMC_NAND_DATA_0); 116 writeb(0x7a, GPMC_NAND_COMMAND_0); 117 writeb(0x00, GPMC_NAND_ADDRESS_0); 118 writeb(0x00, GPMC_NAND_ADDRESS_0); 119 writeb(0x00, GPMC_NAND_ADDRESS_0); 120 writeb(-1, GPMC_NAND_COMMAND_0); 121 122 /* Begin address 0 */ 123 writeb(NAND_CMD_UNLOCK1, 0x6e00007c); 124 writeb(0x00, GPMC_NAND_ADDRESS_0); 125 writeb(0x00, GPMC_NAND_ADDRESS_0); 126 writeb(0x00, GPMC_NAND_ADDRESS_0); 127 writeb(-1, GPMC_NAND_DATA_0); 128 129 /* Ending address at the end of Flash */ 130 writeb(NAND_CMD_UNLOCK2, GPMC_NAND_COMMAND_0); 131 writeb(0xc0, GPMC_NAND_ADDRESS_0); 132 writeb(0xff, GPMC_NAND_ADDRESS_0); 133 writeb(0x03, GPMC_NAND_ADDRESS_0); 134 writeb(-1, GPMC_NAND_DATA_0); 135 writeb(0x79, GPMC_NAND_COMMAND_0); 136 writeb(-1, GPMC_NAND_DATA_0); 137 writeb(-1, GPMC_NAND_DATA_0); 138 } 139 #endif 140 141 #ifdef CONFIG_USB_MUSB_OMAP2PLUS 142 static struct musb_hdrc_config musb_config = { 143 .multipoint = 1, 144 .dyn_fifo = 1, 145 .num_eps = 16, 146 .ram_bits = 12, 147 }; 148 149 static struct omap_musb_board_data musb_board_data = { 150 .interface_type = MUSB_INTERFACE_ULPI, 151 }; 152 153 static struct musb_hdrc_platform_data musb_plat = { 154 #if defined(CONFIG_USB_MUSB_HOST) 155 .mode = MUSB_HOST, 156 #elif defined(CONFIG_USB_MUSB_GADGET) 157 .mode = MUSB_PERIPHERAL, 158 #else 159 #error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET" 160 #endif 161 .config = &musb_config, 162 .power = 100, 163 .platform_ops = &omap2430_ops, 164 .board_data = &musb_board_data, 165 }; 166 #endif 167 168 #if defined(CONFIG_USB_EHCI_HCD) && !defined(CONFIG_SPL_BUILD) 169 /* Call usb_stop() before starting the kernel */ 170 void show_boot_progress(int val) 171 { 172 if (val == BOOTSTAGE_ID_RUN_OS) 173 usb_stop(); 174 } 175 176 static struct omap_usbhs_board_data usbhs_bdata = { 177 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, 178 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, 179 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED 180 }; 181 182 int ehci_hcd_init(int index, enum usb_init_type init, 183 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 184 { 185 return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); 186 } 187 188 int ehci_hcd_stop(int index) 189 { 190 return omap_ehci_hcd_stop(); 191 } 192 193 #endif /* CONFIG_USB_EHCI_HCD */ 194 195 /* 196 * Routine: misc_init_r 197 * Description: Configure board specific parts 198 */ 199 int misc_init_r(void) 200 { 201 twl4030_power_init(); 202 omap_die_id_display(); 203 204 #ifdef CONFIG_USB_MUSB_OMAP2PLUS 205 musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE); 206 #endif 207 208 return 0; 209 } 210 211 /* 212 * Routine: board_init 213 * Description: Early hardware init. 214 */ 215 int board_init(void) 216 { 217 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ 218 219 /* boot param addr */ 220 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 221 222 return 0; 223 } 224 225 #ifdef CONFIG_BOARD_LATE_INIT 226 227 static void unlock_nand(void) 228 { 229 int dev = nand_curr_device; 230 struct mtd_info *mtd; 231 232 mtd = get_nand_dev_by_index(dev); 233 nand_unlock(mtd, 0, mtd->size, 0); 234 } 235 236 int board_late_init(void) 237 { 238 #ifdef CONFIG_CMD_NAND_LOCK_UNLOCK 239 unlock_nand(); 240 #endif 241 return 0; 242 } 243 #endif 244 245 #if defined(CONFIG_MMC) 246 void board_mmc_power_init(void) 247 { 248 twl4030_power_mmc_init(0); 249 } 250 #endif 251 252 #ifdef CONFIG_SMC911X 253 /* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */ 254 static const u32 gpmc_lan92xx_config[] = { 255 NET_LAN92XX_GPMC_CONFIG1, 256 NET_LAN92XX_GPMC_CONFIG2, 257 NET_LAN92XX_GPMC_CONFIG3, 258 NET_LAN92XX_GPMC_CONFIG4, 259 NET_LAN92XX_GPMC_CONFIG5, 260 NET_LAN92XX_GPMC_CONFIG6, 261 }; 262 263 int board_eth_init(bd_t *bis) 264 { 265 enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1], 266 CONFIG_SMC911X_BASE, GPMC_SIZE_16M); 267 268 return smc911x_initialize(0, CONFIG_SMC911X_BASE); 269 } 270 #endif 271