1 /* 2 * (C) Copyright 2011 3 * Logic Product Development <www.logicpd.com> 4 * 5 * Author : 6 * Peter Barada <peter.barada@logicpd.com> 7 * 8 * Derived from Beagle Board and 3430 SDP code by 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * Syed Mohammed Khasim <khasim@ti.com> 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 #include <common.h> 15 #include <netdev.h> 16 #include <flash.h> 17 #include <nand.h> 18 #include <i2c.h> 19 #include <twl4030.h> 20 #include <asm/io.h> 21 #include <asm/arch/mmc_host_def.h> 22 #include <asm/arch/mux.h> 23 #include <asm/arch/mem.h> 24 #include <asm/arch/sys_proto.h> 25 #include <asm/gpio.h> 26 #include <asm/mach-types.h> 27 #include "omap3logic.h" 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 /* 32 * two dimensional array of strucures containining board name and Linux 33 * machine IDs; row it selected based on CPU column is slected based 34 * on hsusb0_data5 pin having a pulldown resistor 35 */ 36 static struct board_id { 37 char *name; 38 int machine_id; 39 } boards[2][2] = { 40 { 41 { 42 .name = "OMAP35xx SOM LV", 43 .machine_id = MACH_TYPE_OMAP3530_LV_SOM, 44 }, 45 { 46 .name = "OMAP35xx Torpedo", 47 .machine_id = MACH_TYPE_OMAP3_TORPEDO, 48 }, 49 }, 50 { 51 { 52 .name = "DM37xx SOM LV", 53 .machine_id = MACH_TYPE_DM3730_SOM_LV, 54 }, 55 { 56 .name = "DM37xx Torpedo", 57 .machine_id = MACH_TYPE_DM3730_TORPEDO, 58 }, 59 }, 60 }; 61 62 /* 63 * BOARD_ID_GPIO - GPIO of pin with optional pulldown resistor on SOM LV 64 */ 65 #define BOARD_ID_GPIO 189 /* hsusb0_data5 pin */ 66 67 /* 68 * Routine: board_init 69 * Description: Early hardware init. 70 */ 71 int board_init(void) 72 { 73 struct board_id *board; 74 unsigned int val; 75 76 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ 77 78 /* boot param addr */ 79 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 80 81 /* 82 * To identify between a SOM LV and Torpedo module, 83 * a pulldown resistor is on hsusb0_data5 for the SOM LV module. 84 * Drive the pin (and let it soak), then read it back. 85 * If the pin is still high its a Torpedo. If low its a SOM LV 86 */ 87 88 /* Mux hsusb0_data5 as a GPIO */ 89 MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M4)); 90 91 if (gpio_request(BOARD_ID_GPIO, "husb0_data5.gpio_189") == 0) { 92 93 /* 94 * Drive BOARD_ID_GPIO - the pulldown resistor on the SOM LV 95 * will drain the voltage. 96 */ 97 gpio_direction_output(BOARD_ID_GPIO, 0); 98 gpio_set_value(BOARD_ID_GPIO, 1); 99 100 /* Let it soak for a bit */ 101 sdelay(0x100); 102 103 /* 104 * Read state of BOARD_ID_GPIO as an input and if its set. 105 * If so the board is a Torpedo 106 */ 107 gpio_direction_input(BOARD_ID_GPIO); 108 val = gpio_get_value(BOARD_ID_GPIO); 109 gpio_free(BOARD_ID_GPIO); 110 111 board = &boards[!!(get_cpu_family() == CPU_OMAP36XX)][!!val]; 112 printf("Board: %s\n", board->name); 113 114 /* Set the machine_id passed to Linux */ 115 gd->bd->bi_arch_number = board->machine_id; 116 } 117 118 /* restore hsusb0_data5 pin as hsusb0_data5 */ 119 MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); 120 121 return 0; 122 } 123 124 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) 125 int board_mmc_init(bd_t *bis) 126 { 127 return omap_mmc_init(0, 0, 0, -1, -1); 128 } 129 #endif 130 131 #ifdef CONFIG_SMC911X 132 /* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */ 133 static const u32 gpmc_lan92xx_config[] = { 134 NET_LAN92XX_GPMC_CONFIG1, 135 NET_LAN92XX_GPMC_CONFIG2, 136 NET_LAN92XX_GPMC_CONFIG3, 137 NET_LAN92XX_GPMC_CONFIG4, 138 NET_LAN92XX_GPMC_CONFIG5, 139 NET_LAN92XX_GPMC_CONFIG6, 140 }; 141 142 int board_eth_init(bd_t *bis) 143 { 144 enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1], 145 CONFIG_SMC911X_BASE, GPMC_SIZE_16M); 146 147 return smc911x_initialize(0, CONFIG_SMC911X_BASE); 148 } 149 #endif 150 151 /* 152 * IEN - Input Enable 153 * IDIS - Input Disable 154 * PTD - Pull type Down 155 * PTU - Pull type Up 156 * DIS - Pull type selection is inactive 157 * EN - Pull type selection is active 158 * M0 - Mode 0 159 * The commented string gives the final mux configuration for that pin 160 */ 161 162 /* 163 * Routine: set_muxconf_regs 164 * Description: Setting up the configuration Mux registers specific to the 165 * hardware. Many pins need to be moved from protect to primary 166 * mode. 167 */ 168 void set_muxconf_regs(void) 169 { 170 /*GPMC*/ 171 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); 172 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); 173 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); 174 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); 175 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); 176 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); 177 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); 178 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); 179 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); 180 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); 181 MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); 182 MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); 183 MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); 184 MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); 185 MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); 186 MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); 187 MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); 188 MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); 189 MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); 190 MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); 191 MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); 192 MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); 193 MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); 194 MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); 195 MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); 196 MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); 197 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); 198 MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)); 199 MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)); 200 MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M0)); 201 MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M4)); 202 MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | DIS | M1)); /*GPMC_IO_DIR*/ 203 MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); 204 MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)); 205 206 /*Expansion card */ 207 MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); 208 MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); 209 MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); 210 MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); 211 MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); 212 MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); 213 214 /* Serial Console */ 215 MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)); 216 MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)); 217 MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)); 218 MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)); 219 220 /* I2C */ 221 MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); 222 MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); 223 MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); 224 MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); 225 226 MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)); 227 228 /*Control and debug */ 229 MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); 230 MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); 231 MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); 232 MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)); 233 MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)); 234 MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); 235 } 236