1 /* 2 * Copyright (C) 2017 Logic PD, Inc. 3 * 4 * Author: Adam Ford <aford173@gmail.com> 5 * 6 * Based on SabreSD by Fabio Estevam <fabio.estevam@nxp.com> 7 * and updates by Jagan Teki <jagan@amarulasolutions.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <miiphy.h> 14 #include <mmc.h> 15 #include <fsl_esdhc.h> 16 #include <asm/io.h> 17 #include <asm/gpio.h> 18 #include <linux/sizes.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/crm_regs.h> 21 #include <asm/arch/iomux.h> 22 #include <asm/arch/mxc_hdmi.h> 23 #include <asm/arch/mx6-pins.h> 24 #include <asm/arch/sys_proto.h> 25 #include <asm/mach-imx/boot_mode.h> 26 #include <asm/mach-imx/iomux-v3.h> 27 28 DECLARE_GLOBAL_DATA_PTR; 29 30 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 31 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 32 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 33 34 #define NAND_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 35 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 36 PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 37 38 int dram_init(void) 39 { 40 gd->ram_size = imx_ddr_size(); 41 return 0; 42 } 43 44 static iomux_v3_cfg_t const uart1_pads[] = { 45 MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 46 MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 47 }; 48 49 static iomux_v3_cfg_t const uart2_pads[] = { 50 MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 51 MX6_PAD_SD4_DAT5__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), 52 MX6_PAD_SD4_DAT6__UART2_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), 53 MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 54 }; 55 56 static iomux_v3_cfg_t const uart3_pads[] = { 57 MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), 58 MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 59 MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 60 MX6_PAD_EIM_EB3__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), 61 }; 62 63 static void fixup_enet_clock(void) 64 { 65 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 66 struct gpio_desc nint; 67 struct gpio_desc reset; 68 int ret; 69 70 /* Set Ref Clock to 50 MHz */ 71 enable_fec_anatop_clock(0, ENET_50MHZ); 72 73 /* Set GPIO_16 as ENET_REF_CLK_OUT */ 74 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); 75 76 /* Request GPIO Pins to reset Ethernet with new clock */ 77 ret = dm_gpio_lookup_name("GPIO4_7", &nint); 78 if (ret) { 79 printf("Unable to lookup GPIO4_7\n"); 80 return; 81 } 82 83 ret = dm_gpio_request(&nint, "eth0_nInt"); 84 if (ret) { 85 printf("Unable to request eth0_nInt\n"); 86 return; 87 } 88 89 /* Ensure nINT is input or PHY won't startup */ 90 dm_gpio_set_dir_flags(&nint, GPIOD_IS_IN); 91 92 ret = dm_gpio_lookup_name("GPIO4_9", &reset); 93 if (ret) { 94 printf("Unable to lookup GPIO4_9\n"); 95 return; 96 } 97 98 ret = dm_gpio_request(&reset, "eth0_reset"); 99 if (ret) { 100 printf("Unable to request eth0_reset\n"); 101 return; 102 } 103 104 /* Reset LAN8710A PHY */ 105 dm_gpio_set_dir_flags(&reset, GPIOD_IS_OUT); 106 dm_gpio_set_value(&reset, 0); 107 udelay(150); 108 dm_gpio_set_value(&reset, 1); 109 mdelay(50); 110 } 111 112 static void setup_iomux_uart(void) 113 { 114 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 115 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); 116 imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); 117 } 118 119 static iomux_v3_cfg_t const nand_pads[] = { 120 MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 121 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), 122 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), 123 MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 124 MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 125 MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), 126 MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), 127 MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), 128 MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), 129 MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), 130 MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), 131 MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), 132 MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), 133 MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 134 MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 135 }; 136 137 static void setup_nand_pins(void) 138 { 139 imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads)); 140 } 141 142 int board_phy_config(struct phy_device *phydev) 143 { 144 if (phydev->drv->config) 145 phydev->drv->config(phydev); 146 147 return 0; 148 } 149 150 /* 151 * Do not overwrite the console 152 * Use always serial for U-Boot console 153 */ 154 int overwrite_console(void) 155 { 156 return 1; 157 } 158 159 int board_early_init_f(void) 160 { 161 fixup_enet_clock(); 162 setup_iomux_uart(); 163 setup_nand_pins(); 164 return 0; 165 } 166 167 int board_init(void) 168 { 169 /* address of boot parameters */ 170 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 171 return 0; 172 } 173 174 int board_late_init(void) 175 { 176 setenv("board_name", "imx6logic"); 177 178 if (is_mx6dq()) { 179 setenv("board_rev", "MX6DQ"); 180 setenv("fdt_file", "imx6q-logicpd.dtb"); 181 } 182 183 return 0; 184 } 185