1 /* 2 * Copyright (C) 2017 Logic PD, Inc. 3 * 4 * Author: Adam Ford <aford173@gmail.com> 5 * 6 * Based on SabreSD by Fabio Estevam <fabio.estevam@nxp.com> 7 * and updates by Jagan Teki <jagan@amarulasolutions.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <miiphy.h> 14 #include <input.h> 15 #include <mmc.h> 16 #include <fsl_esdhc.h> 17 #include <asm/io.h> 18 #include <asm/gpio.h> 19 #include <linux/sizes.h> 20 #include <asm/arch/clock.h> 21 #include <asm/arch/crm_regs.h> 22 #include <asm/arch/iomux.h> 23 #include <asm/arch/mxc_hdmi.h> 24 #include <asm/arch/mx6-pins.h> 25 #include <asm/arch/sys_proto.h> 26 #include <asm/mach-imx/boot_mode.h> 27 #include <asm/mach-imx/iomux-v3.h> 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 32 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 33 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 34 35 #define NAND_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 36 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 37 PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 38 39 int dram_init(void) 40 { 41 gd->ram_size = imx_ddr_size(); 42 return 0; 43 } 44 45 static iomux_v3_cfg_t const uart1_pads[] = { 46 MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 47 MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 48 }; 49 50 static iomux_v3_cfg_t const uart2_pads[] = { 51 MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 52 MX6_PAD_SD4_DAT5__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), 53 MX6_PAD_SD4_DAT6__UART2_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), 54 MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 55 }; 56 57 static iomux_v3_cfg_t const uart3_pads[] = { 58 MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), 59 MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 60 MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 61 MX6_PAD_EIM_EB3__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), 62 }; 63 64 static void fixup_enet_clock(void) 65 { 66 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 67 struct gpio_desc nint; 68 struct gpio_desc reset; 69 int ret; 70 71 /* Set Ref Clock to 50 MHz */ 72 enable_fec_anatop_clock(0, ENET_50MHZ); 73 74 /* Set GPIO_16 as ENET_REF_CLK_OUT */ 75 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); 76 77 /* Request GPIO Pins to reset Ethernet with new clock */ 78 ret = dm_gpio_lookup_name("GPIO4_7", &nint); 79 if (ret) { 80 printf("Unable to lookup GPIO4_7\n"); 81 return; 82 } 83 84 ret = dm_gpio_request(&nint, "eth0_nInt"); 85 if (ret) { 86 printf("Unable to request eth0_nInt\n"); 87 return; 88 } 89 90 /* Ensure nINT is input or PHY won't startup */ 91 dm_gpio_set_dir_flags(&nint, GPIOD_IS_IN); 92 93 ret = dm_gpio_lookup_name("GPIO4_9", &reset); 94 if (ret) { 95 printf("Unable to lookup GPIO4_9\n"); 96 return; 97 } 98 99 ret = dm_gpio_request(&reset, "eth0_reset"); 100 if (ret) { 101 printf("Unable to request eth0_reset\n"); 102 return; 103 } 104 105 /* Reset LAN8710A PHY */ 106 dm_gpio_set_dir_flags(&reset, GPIOD_IS_OUT); 107 dm_gpio_set_value(&reset, 0); 108 udelay(150); 109 dm_gpio_set_value(&reset, 1); 110 mdelay(50); 111 } 112 113 static void setup_iomux_uart(void) 114 { 115 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 116 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); 117 imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); 118 } 119 120 static iomux_v3_cfg_t const nand_pads[] = { 121 MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 122 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), 123 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), 124 MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 125 MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 126 MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), 127 MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), 128 MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), 129 MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), 130 MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), 131 MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), 132 MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), 133 MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), 134 MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 135 MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 136 }; 137 138 static void setup_nand_pins(void) 139 { 140 imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads)); 141 } 142 143 int board_phy_config(struct phy_device *phydev) 144 { 145 if (phydev->drv->config) 146 phydev->drv->config(phydev); 147 148 return 0; 149 } 150 151 /* 152 * Do not overwrite the console 153 * Use always serial for U-Boot console 154 */ 155 int overwrite_console(void) 156 { 157 return 1; 158 } 159 160 int board_early_init_f(void) 161 { 162 fixup_enet_clock(); 163 setup_iomux_uart(); 164 setup_nand_pins(); 165 return 0; 166 } 167 168 int board_init(void) 169 { 170 /* address of boot parameters */ 171 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 172 return 0; 173 } 174 175 int board_late_init(void) 176 { 177 env_set("board_name", "imx6logic"); 178 179 if (is_mx6dq()) { 180 env_set("board_rev", "MX6DQ"); 181 env_set("fdt_file", "imx6q-logicpd.dtb"); 182 } 183 184 return 0; 185 } 186