1*ed01e45cSVaibhav Hiremath /* 2*ed01e45cSVaibhav Hiremath * am3517evm.h - Header file for the AM3517 EVM. 3*ed01e45cSVaibhav Hiremath * 4*ed01e45cSVaibhav Hiremath * Author: Vaibhav Hiremath <hvaibhav@ti.com> 5*ed01e45cSVaibhav Hiremath * 6*ed01e45cSVaibhav Hiremath * Based on ti/evm/evm.h 7*ed01e45cSVaibhav Hiremath * 8*ed01e45cSVaibhav Hiremath * Copyright (C) 2010 9*ed01e45cSVaibhav Hiremath * Texas Instruments Incorporated - http://www.ti.com/ 10*ed01e45cSVaibhav Hiremath * 11*ed01e45cSVaibhav Hiremath * This program is free software; you can redistribute it and/or modify 12*ed01e45cSVaibhav Hiremath * it under the terms of the GNU General Public License as published by 13*ed01e45cSVaibhav Hiremath * the Free Software Foundation; either version 2 of the License, or 14*ed01e45cSVaibhav Hiremath * (at your option) any later version. 15*ed01e45cSVaibhav Hiremath * 16*ed01e45cSVaibhav Hiremath * This program is distributed in the hope that it will be useful, 17*ed01e45cSVaibhav Hiremath * but WITHOUT ANY WARRANTY; without even the implied warranty of 18*ed01e45cSVaibhav Hiremath * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19*ed01e45cSVaibhav Hiremath * GNU General Public License for more details. 20*ed01e45cSVaibhav Hiremath * 21*ed01e45cSVaibhav Hiremath * You should have received a copy of the GNU General Public License 22*ed01e45cSVaibhav Hiremath * along with this program; if not, write to the Free Software 23*ed01e45cSVaibhav Hiremath * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 24*ed01e45cSVaibhav Hiremath */ 25*ed01e45cSVaibhav Hiremath 26*ed01e45cSVaibhav Hiremath #ifndef _AM3517EVM_H_ 27*ed01e45cSVaibhav Hiremath #define _AM3517EVM_H_ 28*ed01e45cSVaibhav Hiremath 29*ed01e45cSVaibhav Hiremath const omap3_sysinfo sysinfo = { 30*ed01e45cSVaibhav Hiremath DDR_DISCRETE, 31*ed01e45cSVaibhav Hiremath "AM3517EVM Board", 32*ed01e45cSVaibhav Hiremath "NAND", 33*ed01e45cSVaibhav Hiremath }; 34*ed01e45cSVaibhav Hiremath /* AM3517 specific mux configuration */ 35*ed01e45cSVaibhav Hiremath #define CONTROL_PADCONF_SYS_NRESWARM 0x0A08 36*ed01e45cSVaibhav Hiremath /* CCDC */ 37*ed01e45cSVaibhav Hiremath #define CONTROL_PADCONF_CCDC_PCLK 0x01E4 38*ed01e45cSVaibhav Hiremath #define CONTROL_PADCONF_CCDC_FIELD 0x01E6 39*ed01e45cSVaibhav Hiremath #define CONTROL_PADCONF_CCDC_HD 0x01E8 40*ed01e45cSVaibhav Hiremath #define CONTROL_PADCONF_CCDC_VD 0x01EA 41*ed01e45cSVaibhav Hiremath #define CONTROL_PADCONF_CCDC_WEN 0x01EC 42*ed01e45cSVaibhav Hiremath #define CONTROL_PADCONF_CCDC_DATA0 0x01EE 43*ed01e45cSVaibhav Hiremath #define CONTROL_PADCONF_CCDC_DATA1 0x01F0 44*ed01e45cSVaibhav Hiremath #define CONTROL_PADCONF_CCDC_DATA2 0x01F2 45*ed01e45cSVaibhav Hiremath #define CONTROL_PADCONF_CCDC_DATA3 0x01F4 46*ed01e45cSVaibhav Hiremath #define CONTROL_PADCONF_CCDC_DATA4 0x01F6 47*ed01e45cSVaibhav Hiremath #define CONTROL_PADCONF_CCDC_DATA5 0x01F8 48*ed01e45cSVaibhav Hiremath #define CONTROL_PADCONF_CCDC_DATA6 0x01FA 49*ed01e45cSVaibhav Hiremath #define CONTROL_PADCONF_CCDC_DATA7 0x01FC 50*ed01e45cSVaibhav Hiremath /* RMII */ 51*ed01e45cSVaibhav Hiremath #define CONTROL_PADCONF_RMII_MDIO_DATA 0x01FE 52*ed01e45cSVaibhav Hiremath #define CONTROL_PADCONF_RMII_MDIO_CLK 0x0200 53*ed01e45cSVaibhav Hiremath #define CONTROL_PADCONF_RMII_RXD0 0x0202 54*ed01e45cSVaibhav Hiremath #define CONTROL_PADCONF_RMII_RXD1 0x0204 55*ed01e45cSVaibhav Hiremath #define CONTROL_PADCONF_RMII_CRS_DV 0x0206 56*ed01e45cSVaibhav Hiremath #define CONTROL_PADCONF_RMII_RXER 0x0208 57*ed01e45cSVaibhav Hiremath #define CONTROL_PADCONF_RMII_TXD0 0x020A 58*ed01e45cSVaibhav Hiremath #define CONTROL_PADCONF_RMII_TXD1 0x020C 59*ed01e45cSVaibhav Hiremath #define CONTROL_PADCONF_RMII_TXEN 0x020E 60*ed01e45cSVaibhav Hiremath #define CONTROL_PADCONF_RMII_50MHZ_CLK 0x0210 61*ed01e45cSVaibhav Hiremath #define CONTROL_PADCONF_USB0_DRVBUS 0x0212 62*ed01e45cSVaibhav Hiremath /* CAN */ 63*ed01e45cSVaibhav Hiremath #define CONTROL_PADCONF_HECC1_TXD 0x0214 64*ed01e45cSVaibhav Hiremath #define CONTROL_PADCONF_HECC1_RXD 0x0216 65*ed01e45cSVaibhav Hiremath 66*ed01e45cSVaibhav Hiremath #define CONTROL_PADCONF_SYS_BOOT7 0x0218 67*ed01e45cSVaibhav Hiremath #define CONTROL_PADCONF_SDRC_DQS0N 0x021A 68*ed01e45cSVaibhav Hiremath #define CONTROL_PADCONF_SDRC_DQS1N 0x021C 69*ed01e45cSVaibhav Hiremath #define CONTROL_PADCONF_SDRC_DQS2N 0x021E 70*ed01e45cSVaibhav Hiremath #define CONTROL_PADCONF_SDRC_DQS3N 0x0220 71*ed01e45cSVaibhav Hiremath #define CONTROL_PADCONF_STRBEN_DLY0 0x0222 72*ed01e45cSVaibhav Hiremath #define CONTROL_PADCONF_STRBEN_DLY1 0x0224 73*ed01e45cSVaibhav Hiremath #define CONTROL_PADCONF_SYS_BOOT8 0x0226 74*ed01e45cSVaibhav Hiremath 75*ed01e45cSVaibhav Hiremath /* 76*ed01e45cSVaibhav Hiremath * IEN - Input Enable 77*ed01e45cSVaibhav Hiremath * IDIS - Input Disable 78*ed01e45cSVaibhav Hiremath * PTD - Pull type Down 79*ed01e45cSVaibhav Hiremath * PTU - Pull type Up 80*ed01e45cSVaibhav Hiremath * DIS - Pull type selection is inactive 81*ed01e45cSVaibhav Hiremath * EN - Pull type selection is active 82*ed01e45cSVaibhav Hiremath * M0 - Mode 0 83*ed01e45cSVaibhav Hiremath * The commented string gives the final mux configuration for that pin 84*ed01e45cSVaibhav Hiremath */ 85*ed01e45cSVaibhav Hiremath #define MUX_AM3517EVM() \ 86*ed01e45cSVaibhav Hiremath /* SDRC */\ 87*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \ 88*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \ 89*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \ 90*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \ 91*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \ 92*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \ 93*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \ 94*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \ 95*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \ 96*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \ 97*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \ 98*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \ 99*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \ 100*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \ 101*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \ 102*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \ 103*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \ 104*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \ 105*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \ 106*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \ 107*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \ 108*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \ 109*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \ 110*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \ 111*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \ 112*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \ 113*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \ 114*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \ 115*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \ 116*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \ 117*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \ 118*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \ 119*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \ 120*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \ 121*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \ 122*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \ 123*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \ 124*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \ 125*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \ 126*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \ 127*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \ 128*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_CKE0), (M0)) \ 129*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SDRC_CKE1), (M0)) \ 130*ed01e45cSVaibhav Hiremath /*sdrc_strben_dly0*/\ 131*ed01e45cSVaibhav Hiremath MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \ 132*ed01e45cSVaibhav Hiremath /*sdrc_strben_dly1*/\ 133*ed01e45cSVaibhav Hiremath MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \ 134*ed01e45cSVaibhav Hiremath /* GPMC */\ 135*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \ 136*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \ 137*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \ 138*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \ 139*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \ 140*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \ 141*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \ 142*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \ 143*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \ 144*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \ 145*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \ 146*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \ 147*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \ 148*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \ 149*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \ 150*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \ 151*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \ 152*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \ 153*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \ 154*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \ 155*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \ 156*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \ 157*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \ 158*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \ 159*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \ 160*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \ 161*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \ 162*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) \ 163*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) \ 164*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) \ 165*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)) \ 166*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) \ 167*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) \ 168*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) \ 169*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \ 170*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \ 171*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \ 172*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \ 173*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \ 174*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \ 175*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \ 176*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \ 177*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) \ 178*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\ 179*ed01e45cSVaibhav Hiremath /* - ETH_nRESET*/\ 180*ed01e45cSVaibhav Hiremath MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) \ 181*ed01e45cSVaibhav Hiremath /* DSS */\ 182*ed01e45cSVaibhav Hiremath MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \ 183*ed01e45cSVaibhav Hiremath MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \ 184*ed01e45cSVaibhav Hiremath MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \ 185*ed01e45cSVaibhav Hiremath MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \ 186*ed01e45cSVaibhav Hiremath MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \ 187*ed01e45cSVaibhav Hiremath MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \ 188*ed01e45cSVaibhav Hiremath MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \ 189*ed01e45cSVaibhav Hiremath MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \ 190*ed01e45cSVaibhav Hiremath MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \ 191*ed01e45cSVaibhav Hiremath MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \ 192*ed01e45cSVaibhav Hiremath MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \ 193*ed01e45cSVaibhav Hiremath MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \ 194*ed01e45cSVaibhav Hiremath MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \ 195*ed01e45cSVaibhav Hiremath MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \ 196*ed01e45cSVaibhav Hiremath MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \ 197*ed01e45cSVaibhav Hiremath MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \ 198*ed01e45cSVaibhav Hiremath MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \ 199*ed01e45cSVaibhav Hiremath MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \ 200*ed01e45cSVaibhav Hiremath MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \ 201*ed01e45cSVaibhav Hiremath MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \ 202*ed01e45cSVaibhav Hiremath MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \ 203*ed01e45cSVaibhav Hiremath MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \ 204*ed01e45cSVaibhav Hiremath MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \ 205*ed01e45cSVaibhav Hiremath MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \ 206*ed01e45cSVaibhav Hiremath MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \ 207*ed01e45cSVaibhav Hiremath MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \ 208*ed01e45cSVaibhav Hiremath MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \ 209*ed01e45cSVaibhav Hiremath MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \ 210*ed01e45cSVaibhav Hiremath /* CAMERA */\ 211*ed01e45cSVaibhav Hiremath MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \ 212*ed01e45cSVaibhav Hiremath MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \ 213*ed01e45cSVaibhav Hiremath MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \ 214*ed01e45cSVaibhav Hiremath MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \ 215*ed01e45cSVaibhav Hiremath MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\ 216*ed01e45cSVaibhav Hiremath /* - CAM_RESET*/\ 217*ed01e45cSVaibhav Hiremath MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \ 218*ed01e45cSVaibhav Hiremath MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \ 219*ed01e45cSVaibhav Hiremath MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \ 220*ed01e45cSVaibhav Hiremath MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \ 221*ed01e45cSVaibhav Hiremath MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \ 222*ed01e45cSVaibhav Hiremath MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \ 223*ed01e45cSVaibhav Hiremath MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \ 224*ed01e45cSVaibhav Hiremath MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \ 225*ed01e45cSVaibhav Hiremath MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \ 226*ed01e45cSVaibhav Hiremath MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \ 227*ed01e45cSVaibhav Hiremath MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \ 228*ed01e45cSVaibhav Hiremath MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \ 229*ed01e45cSVaibhav Hiremath MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \ 230*ed01e45cSVaibhav Hiremath MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ 231*ed01e45cSVaibhav Hiremath MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \ 232*ed01e45cSVaibhav Hiremath MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \ 233*ed01e45cSVaibhav Hiremath MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \ 234*ed01e45cSVaibhav Hiremath MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \ 235*ed01e45cSVaibhav Hiremath MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \ 236*ed01e45cSVaibhav Hiremath /* MMC */\ 237*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \ 238*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \ 239*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \ 240*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \ 241*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \ 242*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \ 243*ed01e45cSVaibhav Hiremath /* WriteProtect */\ 244*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \ 245*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) /*CardDetect*/\ 246*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \ 247*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \ 248*ed01e45cSVaibhav Hiremath \ 249*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M0)) \ 250*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M0)) \ 251*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M0)) \ 252*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | DIS | M0)) \ 253*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | DIS | M0)) \ 254*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | DIS | M0)) \ 255*ed01e45cSVaibhav Hiremath /* McBSP */\ 256*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \ 257*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \ 258*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \ 259*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \ 260*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \ 261*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \ 262*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \ 263*ed01e45cSVaibhav Hiremath \ 264*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) \ 265*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) \ 266*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) \ 267*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) \ 268*ed01e45cSVaibhav Hiremath \ 269*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) \ 270*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) \ 271*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)) \ 272*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) \ 273*ed01e45cSVaibhav Hiremath \ 274*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_152*/\ 275*ed01e45cSVaibhav Hiremath /* - LCD_INI*/\ 276*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\ 277*ed01e45cSVaibhav Hiremath /* - LCD_ENVDD */\ 278*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\ 279*ed01e45cSVaibhav Hiremath /* - LCD_QVGA/nVGA */\ 280*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_155*/\ 281*ed01e45cSVaibhav Hiremath /* - LCD_RESB */\ 282*ed01e45cSVaibhav Hiremath /* UART */\ 283*ed01e45cSVaibhav Hiremath MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \ 284*ed01e45cSVaibhav Hiremath MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \ 285*ed01e45cSVaibhav Hiremath MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \ 286*ed01e45cSVaibhav Hiremath \ 287*ed01e45cSVaibhav Hiremath MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \ 288*ed01e45cSVaibhav Hiremath MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \ 289*ed01e45cSVaibhav Hiremath MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \ 290*ed01e45cSVaibhav Hiremath MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \ 291*ed01e45cSVaibhav Hiremath MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \ 292*ed01e45cSVaibhav Hiremath \ 293*ed01e45cSVaibhav Hiremath MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \ 294*ed01e45cSVaibhav Hiremath MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \ 295*ed01e45cSVaibhav Hiremath MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \ 296*ed01e45cSVaibhav Hiremath MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \ 297*ed01e45cSVaibhav Hiremath /* I2C */\ 298*ed01e45cSVaibhav Hiremath MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \ 299*ed01e45cSVaibhav Hiremath MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \ 300*ed01e45cSVaibhav Hiremath MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \ 301*ed01e45cSVaibhav Hiremath MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \ 302*ed01e45cSVaibhav Hiremath MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \ 303*ed01e45cSVaibhav Hiremath MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \ 304*ed01e45cSVaibhav Hiremath MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \ 305*ed01e45cSVaibhav Hiremath MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \ 306*ed01e45cSVaibhav Hiremath /* McSPI */\ 307*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \ 308*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \ 309*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \ 310*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \ 311*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\ 312*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176*/\ 313*ed01e45cSVaibhav Hiremath /* - LAN_INTR*/\ 314*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) \ 315*ed01e45cSVaibhav Hiremath \ 316*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \ 317*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \ 318*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \ 319*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \ 320*ed01e45cSVaibhav Hiremath MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M4)) \ 321*ed01e45cSVaibhav Hiremath /* CCDC */\ 322*ed01e45cSVaibhav Hiremath MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0)) \ 323*ed01e45cSVaibhav Hiremath MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1)) \ 324*ed01e45cSVaibhav Hiremath MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0)) \ 325*ed01e45cSVaibhav Hiremath MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0)) \ 326*ed01e45cSVaibhav Hiremath MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1)) \ 327*ed01e45cSVaibhav Hiremath MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0)) \ 328*ed01e45cSVaibhav Hiremath MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0)) \ 329*ed01e45cSVaibhav Hiremath MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0)) \ 330*ed01e45cSVaibhav Hiremath MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0)) \ 331*ed01e45cSVaibhav Hiremath MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0)) \ 332*ed01e45cSVaibhav Hiremath MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0)) \ 333*ed01e45cSVaibhav Hiremath MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0)) \ 334*ed01e45cSVaibhav Hiremath MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0)) \ 335*ed01e45cSVaibhav Hiremath /* RMII */\ 336*ed01e45cSVaibhav Hiremath MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \ 337*ed01e45cSVaibhav Hiremath MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \ 338*ed01e45cSVaibhav Hiremath MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \ 339*ed01e45cSVaibhav Hiremath MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \ 340*ed01e45cSVaibhav Hiremath MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \ 341*ed01e45cSVaibhav Hiremath MUX_VAL(CP(RMII_RXER), (PTD | M0)) \ 342*ed01e45cSVaibhav Hiremath MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \ 343*ed01e45cSVaibhav Hiremath MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \ 344*ed01e45cSVaibhav Hiremath MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \ 345*ed01e45cSVaibhav Hiremath MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \ 346*ed01e45cSVaibhav Hiremath /* HECC */\ 347*ed01e45cSVaibhav Hiremath MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \ 348*ed01e45cSVaibhav Hiremath MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \ 349*ed01e45cSVaibhav Hiremath /* HSUSB */\ 350*ed01e45cSVaibhav Hiremath MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \ 351*ed01e45cSVaibhav Hiremath MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \ 352*ed01e45cSVaibhav Hiremath MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \ 353*ed01e45cSVaibhav Hiremath MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \ 354*ed01e45cSVaibhav Hiremath MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \ 355*ed01e45cSVaibhav Hiremath MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \ 356*ed01e45cSVaibhav Hiremath MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \ 357*ed01e45cSVaibhav Hiremath MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \ 358*ed01e45cSVaibhav Hiremath MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \ 359*ed01e45cSVaibhav Hiremath MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \ 360*ed01e45cSVaibhav Hiremath MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \ 361*ed01e45cSVaibhav Hiremath MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \ 362*ed01e45cSVaibhav Hiremath MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \ 363*ed01e45cSVaibhav Hiremath /* HDQ */\ 364*ed01e45cSVaibhav Hiremath MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) \ 365*ed01e45cSVaibhav Hiremath /* Control and debug */\ 366*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \ 367*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \ 368*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \ 369*ed01e45cSVaibhav Hiremath /*SYS_nRESWARM */\ 370*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \ 371*ed01e45cSVaibhav Hiremath /* - GPIO30 */\ 372*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\ 373*ed01e45cSVaibhav Hiremath /* - PEN_IRQ */\ 374*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ 375*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\ 376*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\ 377*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\ 378*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\ 379*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\ 380*ed01e45cSVaibhav Hiremath /* - VIO_1V8*/\ 381*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \ 382*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \ 383*ed01e45cSVaibhav Hiremath \ 384*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \ 385*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \ 386*ed01e45cSVaibhav Hiremath MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \ 387*ed01e45cSVaibhav Hiremath /* JTAG */\ 388*ed01e45cSVaibhav Hiremath MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \ 389*ed01e45cSVaibhav Hiremath MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \ 390*ed01e45cSVaibhav Hiremath MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \ 391*ed01e45cSVaibhav Hiremath MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \ 392*ed01e45cSVaibhav Hiremath MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) \ 393*ed01e45cSVaibhav Hiremath MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) \ 394*ed01e45cSVaibhav Hiremath /* ETK (ES2 onwards) */\ 395*ed01e45cSVaibhav Hiremath MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)) \ 396*ed01e45cSVaibhav Hiremath MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)) \ 397*ed01e45cSVaibhav Hiremath MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)) \ 398*ed01e45cSVaibhav Hiremath MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)) \ 399*ed01e45cSVaibhav Hiremath MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)) \ 400*ed01e45cSVaibhav Hiremath MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)) \ 401*ed01e45cSVaibhav Hiremath MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)) \ 402*ed01e45cSVaibhav Hiremath MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)) \ 403*ed01e45cSVaibhav Hiremath MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)) \ 404*ed01e45cSVaibhav Hiremath MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)) \ 405*ed01e45cSVaibhav Hiremath MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)) \ 406*ed01e45cSVaibhav Hiremath MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)) \ 407*ed01e45cSVaibhav Hiremath MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)) \ 408*ed01e45cSVaibhav Hiremath MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)) \ 409*ed01e45cSVaibhav Hiremath MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)) \ 410*ed01e45cSVaibhav Hiremath MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)) \ 411*ed01e45cSVaibhav Hiremath MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)) \ 412*ed01e45cSVaibhav Hiremath MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)) \ 413*ed01e45cSVaibhav Hiremath /* Die to Die */\ 414*ed01e45cSVaibhav Hiremath MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \ 415*ed01e45cSVaibhav Hiremath MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \ 416*ed01e45cSVaibhav Hiremath MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \ 417*ed01e45cSVaibhav Hiremath MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \ 418*ed01e45cSVaibhav Hiremath MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \ 419*ed01e45cSVaibhav Hiremath MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \ 420*ed01e45cSVaibhav Hiremath MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \ 421*ed01e45cSVaibhav Hiremath MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \ 422*ed01e45cSVaibhav Hiremath MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \ 423*ed01e45cSVaibhav Hiremath MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \ 424*ed01e45cSVaibhav Hiremath MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \ 425*ed01e45cSVaibhav Hiremath MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \ 426*ed01e45cSVaibhav Hiremath MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \ 427*ed01e45cSVaibhav Hiremath MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \ 428*ed01e45cSVaibhav Hiremath MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \ 429*ed01e45cSVaibhav Hiremath MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \ 430*ed01e45cSVaibhav Hiremath MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \ 431*ed01e45cSVaibhav Hiremath MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \ 432*ed01e45cSVaibhav Hiremath MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \ 433*ed01e45cSVaibhav Hiremath MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \ 434*ed01e45cSVaibhav Hiremath MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \ 435*ed01e45cSVaibhav Hiremath MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \ 436*ed01e45cSVaibhav Hiremath MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \ 437*ed01e45cSVaibhav Hiremath MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \ 438*ed01e45cSVaibhav Hiremath MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \ 439*ed01e45cSVaibhav Hiremath MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \ 440*ed01e45cSVaibhav Hiremath MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \ 441*ed01e45cSVaibhav Hiremath MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \ 442*ed01e45cSVaibhav Hiremath MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \ 443*ed01e45cSVaibhav Hiremath MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \ 444*ed01e45cSVaibhav Hiremath 445*ed01e45cSVaibhav Hiremath #endif 446