111bd5e7bSLukasz Majewski /* 211bd5e7bSLukasz Majewski * Copyright (C) 2014 Wandboard 311bd5e7bSLukasz Majewski * Author: Tungyi Lin <tungyilin1127@gmail.com> 411bd5e7bSLukasz Majewski * Richard Hu <hakahu@gmail.com> 511bd5e7bSLukasz Majewski * SPDX-License-Identifier: GPL-2.0+ 611bd5e7bSLukasz Majewski */ 711bd5e7bSLukasz Majewski 811bd5e7bSLukasz Majewski #include <asm/arch/clock.h> 911bd5e7bSLukasz Majewski #include <asm/arch/imx-regs.h> 1011bd5e7bSLukasz Majewski #include <asm/arch/iomux.h> 1111bd5e7bSLukasz Majewski #include <asm/arch/mx6-pins.h> 1211bd5e7bSLukasz Majewski #include <errno.h> 1311bd5e7bSLukasz Majewski #include <asm/gpio.h> 14*552a848eSStefano Babic #include <asm/mach-imx/iomux-v3.h> 15*552a848eSStefano Babic #include <asm/mach-imx/video.h> 1611bd5e7bSLukasz Majewski #include <mmc.h> 1711bd5e7bSLukasz Majewski #include <fsl_esdhc.h> 1811bd5e7bSLukasz Majewski #include <asm/arch/crm_regs.h> 1911bd5e7bSLukasz Majewski #include <asm/io.h> 2011bd5e7bSLukasz Majewski #include <asm/arch/sys_proto.h> 2111bd5e7bSLukasz Majewski #include <spl.h> 2211bd5e7bSLukasz Majewski 2311bd5e7bSLukasz Majewski DECLARE_GLOBAL_DATA_PTR; 2411bd5e7bSLukasz Majewski 2511bd5e7bSLukasz Majewski #if defined(CONFIG_SPL_BUILD) 2611bd5e7bSLukasz Majewski #include <asm/arch/mx6-ddr.h> 2711bd5e7bSLukasz Majewski /* 2811bd5e7bSLukasz Majewski * Driving strength: 2911bd5e7bSLukasz Majewski * 0x30 == 40 Ohm 3011bd5e7bSLukasz Majewski * 0x28 == 48 Ohm 3111bd5e7bSLukasz Majewski */ 3211bd5e7bSLukasz Majewski 3311bd5e7bSLukasz Majewski #define IMX6DQ_DRIVE_STRENGTH 0x30 3411bd5e7bSLukasz Majewski #define IMX6SDL_DRIVE_STRENGTH 0x28 3511bd5e7bSLukasz Majewski 3611bd5e7bSLukasz Majewski /* configure MX6Q/DUAL mmdc DDR io registers */ 3711bd5e7bSLukasz Majewski static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { 3811bd5e7bSLukasz Majewski .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH, 3911bd5e7bSLukasz Majewski .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH, 4011bd5e7bSLukasz Majewski .dram_cas = IMX6DQ_DRIVE_STRENGTH, 4111bd5e7bSLukasz Majewski .dram_ras = IMX6DQ_DRIVE_STRENGTH, 4211bd5e7bSLukasz Majewski .dram_reset = IMX6DQ_DRIVE_STRENGTH, 4311bd5e7bSLukasz Majewski .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH, 4411bd5e7bSLukasz Majewski .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH, 4511bd5e7bSLukasz Majewski .dram_sdba2 = 0x00000000, 4611bd5e7bSLukasz Majewski .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH, 4711bd5e7bSLukasz Majewski .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH, 4811bd5e7bSLukasz Majewski .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH, 4911bd5e7bSLukasz Majewski .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH, 5011bd5e7bSLukasz Majewski .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH, 5111bd5e7bSLukasz Majewski .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH, 5211bd5e7bSLukasz Majewski .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH, 5311bd5e7bSLukasz Majewski .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH, 5411bd5e7bSLukasz Majewski .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH, 5511bd5e7bSLukasz Majewski .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH, 5611bd5e7bSLukasz Majewski .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH, 5711bd5e7bSLukasz Majewski .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH, 5811bd5e7bSLukasz Majewski .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH, 5911bd5e7bSLukasz Majewski .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH, 6011bd5e7bSLukasz Majewski .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH, 6111bd5e7bSLukasz Majewski .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH, 6211bd5e7bSLukasz Majewski .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH, 6311bd5e7bSLukasz Majewski .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH, 6411bd5e7bSLukasz Majewski }; 6511bd5e7bSLukasz Majewski 6611bd5e7bSLukasz Majewski /* configure MX6Q/DUAL mmdc GRP io registers */ 6711bd5e7bSLukasz Majewski static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { 6811bd5e7bSLukasz Majewski .grp_ddr_type = 0x000c0000, 6911bd5e7bSLukasz Majewski .grp_ddrmode_ctl = 0x00020000, 7011bd5e7bSLukasz Majewski .grp_ddrpke = 0x00000000, 7111bd5e7bSLukasz Majewski .grp_addds = IMX6DQ_DRIVE_STRENGTH, 7211bd5e7bSLukasz Majewski .grp_ctlds = IMX6DQ_DRIVE_STRENGTH, 7311bd5e7bSLukasz Majewski .grp_ddrmode = 0x00020000, 7411bd5e7bSLukasz Majewski .grp_b0ds = IMX6DQ_DRIVE_STRENGTH, 7511bd5e7bSLukasz Majewski .grp_b1ds = IMX6DQ_DRIVE_STRENGTH, 7611bd5e7bSLukasz Majewski .grp_b2ds = IMX6DQ_DRIVE_STRENGTH, 7711bd5e7bSLukasz Majewski .grp_b3ds = IMX6DQ_DRIVE_STRENGTH, 7811bd5e7bSLukasz Majewski .grp_b4ds = IMX6DQ_DRIVE_STRENGTH, 7911bd5e7bSLukasz Majewski .grp_b5ds = IMX6DQ_DRIVE_STRENGTH, 8011bd5e7bSLukasz Majewski .grp_b6ds = IMX6DQ_DRIVE_STRENGTH, 8111bd5e7bSLukasz Majewski .grp_b7ds = IMX6DQ_DRIVE_STRENGTH, 8211bd5e7bSLukasz Majewski }; 8311bd5e7bSLukasz Majewski 8411bd5e7bSLukasz Majewski /* configure MX6SOLO/DUALLITE mmdc DDR io registers */ 8511bd5e7bSLukasz Majewski struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { 8611bd5e7bSLukasz Majewski .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH, 8711bd5e7bSLukasz Majewski .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH, 8811bd5e7bSLukasz Majewski .dram_cas = IMX6SDL_DRIVE_STRENGTH, 8911bd5e7bSLukasz Majewski .dram_ras = IMX6SDL_DRIVE_STRENGTH, 9011bd5e7bSLukasz Majewski .dram_reset = IMX6SDL_DRIVE_STRENGTH, 9111bd5e7bSLukasz Majewski .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH, 9211bd5e7bSLukasz Majewski .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH, 9311bd5e7bSLukasz Majewski .dram_sdba2 = 0x00000000, 9411bd5e7bSLukasz Majewski .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH, 9511bd5e7bSLukasz Majewski .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH, 9611bd5e7bSLukasz Majewski .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH, 9711bd5e7bSLukasz Majewski .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH, 9811bd5e7bSLukasz Majewski .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH, 9911bd5e7bSLukasz Majewski .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH, 10011bd5e7bSLukasz Majewski .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH, 10111bd5e7bSLukasz Majewski .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH, 10211bd5e7bSLukasz Majewski .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH, 10311bd5e7bSLukasz Majewski .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH, 10411bd5e7bSLukasz Majewski .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH, 10511bd5e7bSLukasz Majewski .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH, 10611bd5e7bSLukasz Majewski .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH, 10711bd5e7bSLukasz Majewski .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH, 10811bd5e7bSLukasz Majewski .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH, 10911bd5e7bSLukasz Majewski .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH, 11011bd5e7bSLukasz Majewski .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH, 11111bd5e7bSLukasz Majewski .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH, 11211bd5e7bSLukasz Majewski }; 11311bd5e7bSLukasz Majewski 11411bd5e7bSLukasz Majewski /* configure MX6SOLO/DUALLITE mmdc GRP io registers */ 11511bd5e7bSLukasz Majewski struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { 11611bd5e7bSLukasz Majewski .grp_ddr_type = 0x000c0000, 11711bd5e7bSLukasz Majewski .grp_ddrmode_ctl = 0x00020000, 11811bd5e7bSLukasz Majewski .grp_ddrpke = 0x00000000, 11911bd5e7bSLukasz Majewski .grp_addds = IMX6SDL_DRIVE_STRENGTH, 12011bd5e7bSLukasz Majewski .grp_ctlds = IMX6SDL_DRIVE_STRENGTH, 12111bd5e7bSLukasz Majewski .grp_ddrmode = 0x00020000, 12211bd5e7bSLukasz Majewski .grp_b0ds = IMX6SDL_DRIVE_STRENGTH, 12311bd5e7bSLukasz Majewski .grp_b1ds = IMX6SDL_DRIVE_STRENGTH, 12411bd5e7bSLukasz Majewski .grp_b2ds = IMX6SDL_DRIVE_STRENGTH, 12511bd5e7bSLukasz Majewski .grp_b3ds = IMX6SDL_DRIVE_STRENGTH, 12611bd5e7bSLukasz Majewski .grp_b4ds = IMX6SDL_DRIVE_STRENGTH, 12711bd5e7bSLukasz Majewski .grp_b5ds = IMX6SDL_DRIVE_STRENGTH, 12811bd5e7bSLukasz Majewski .grp_b6ds = IMX6SDL_DRIVE_STRENGTH, 12911bd5e7bSLukasz Majewski .grp_b7ds = IMX6SDL_DRIVE_STRENGTH, 13011bd5e7bSLukasz Majewski }; 13111bd5e7bSLukasz Majewski 13211bd5e7bSLukasz Majewski /* H5T04G63AFR-PB */ 13311bd5e7bSLukasz Majewski static struct mx6_ddr3_cfg h5t04g63afr = { 13411bd5e7bSLukasz Majewski .mem_speed = 1600, 13511bd5e7bSLukasz Majewski .density = 4, 13611bd5e7bSLukasz Majewski .width = 16, 13711bd5e7bSLukasz Majewski .banks = 8, 13811bd5e7bSLukasz Majewski .rowaddr = 15, 13911bd5e7bSLukasz Majewski .coladdr = 10, 14011bd5e7bSLukasz Majewski .pagesz = 2, 14111bd5e7bSLukasz Majewski .trcd = 1375, 14211bd5e7bSLukasz Majewski .trcmin = 4875, 14311bd5e7bSLukasz Majewski .trasmin = 3500, 14411bd5e7bSLukasz Majewski }; 14511bd5e7bSLukasz Majewski 14611bd5e7bSLukasz Majewski /* H5TQ2G63DFR-H9 */ 14711bd5e7bSLukasz Majewski static struct mx6_ddr3_cfg h5tq2g63dfr = { 14811bd5e7bSLukasz Majewski .mem_speed = 1333, 14911bd5e7bSLukasz Majewski .density = 2, 15011bd5e7bSLukasz Majewski .width = 16, 15111bd5e7bSLukasz Majewski .banks = 8, 15211bd5e7bSLukasz Majewski .rowaddr = 14, 15311bd5e7bSLukasz Majewski .coladdr = 10, 15411bd5e7bSLukasz Majewski .pagesz = 2, 15511bd5e7bSLukasz Majewski .trcd = 1350, 15611bd5e7bSLukasz Majewski .trcmin = 4950, 15711bd5e7bSLukasz Majewski .trasmin = 3600, 15811bd5e7bSLukasz Majewski }; 15911bd5e7bSLukasz Majewski 16011bd5e7bSLukasz Majewski static struct mx6_mmdc_calibration mx6q_2g_mmdc_calib = { 16111bd5e7bSLukasz Majewski .p0_mpwldectrl0 = 0x001f001f, 16211bd5e7bSLukasz Majewski .p0_mpwldectrl1 = 0x001f001f, 16311bd5e7bSLukasz Majewski .p1_mpwldectrl0 = 0x001f001f, 16411bd5e7bSLukasz Majewski .p1_mpwldectrl1 = 0x001f001f, 16511bd5e7bSLukasz Majewski .p0_mpdgctrl0 = 0x4301030d, 16611bd5e7bSLukasz Majewski .p0_mpdgctrl1 = 0x03020277, 16711bd5e7bSLukasz Majewski .p1_mpdgctrl0 = 0x4300030a, 16811bd5e7bSLukasz Majewski .p1_mpdgctrl1 = 0x02780248, 16911bd5e7bSLukasz Majewski .p0_mprddlctl = 0x4536393b, 17011bd5e7bSLukasz Majewski .p1_mprddlctl = 0x36353441, 17111bd5e7bSLukasz Majewski .p0_mpwrdlctl = 0x41414743, 17211bd5e7bSLukasz Majewski .p1_mpwrdlctl = 0x462f453f, 17311bd5e7bSLukasz Majewski }; 17411bd5e7bSLukasz Majewski 17511bd5e7bSLukasz Majewski /* DDR 64bit 2GB */ 17611bd5e7bSLukasz Majewski static struct mx6_ddr_sysinfo mem_q = { 17711bd5e7bSLukasz Majewski .dsize = 2, 17811bd5e7bSLukasz Majewski .cs1_mirror = 0, 17911bd5e7bSLukasz Majewski /* config for full 4GB range so that get_mem_size() works */ 18011bd5e7bSLukasz Majewski .cs_density = 32, 18111bd5e7bSLukasz Majewski .ncs = 1, 18211bd5e7bSLukasz Majewski .bi_on = 1, 18311bd5e7bSLukasz Majewski .rtt_nom = 1, 18411bd5e7bSLukasz Majewski .rtt_wr = 0, 18511bd5e7bSLukasz Majewski .ralat = 5, 18611bd5e7bSLukasz Majewski .walat = 0, 18711bd5e7bSLukasz Majewski .mif3_mode = 3, 18811bd5e7bSLukasz Majewski .rst_to_cke = 0x23, 18911bd5e7bSLukasz Majewski .sde_to_rst = 0x10, 19011bd5e7bSLukasz Majewski }; 19111bd5e7bSLukasz Majewski 19211bd5e7bSLukasz Majewski static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = { 19311bd5e7bSLukasz Majewski .p0_mpwldectrl0 = 0x001f001f, 19411bd5e7bSLukasz Majewski .p0_mpwldectrl1 = 0x001f001f, 19511bd5e7bSLukasz Majewski .p1_mpwldectrl0 = 0x001f001f, 19611bd5e7bSLukasz Majewski .p1_mpwldectrl1 = 0x001f001f, 19711bd5e7bSLukasz Majewski .p0_mpdgctrl0 = 0x420e020e, 19811bd5e7bSLukasz Majewski .p0_mpdgctrl1 = 0x02000200, 19911bd5e7bSLukasz Majewski .p1_mpdgctrl0 = 0x42020202, 20011bd5e7bSLukasz Majewski .p1_mpdgctrl1 = 0x01720172, 20111bd5e7bSLukasz Majewski .p0_mprddlctl = 0x494c4f4c, 20211bd5e7bSLukasz Majewski .p1_mprddlctl = 0x4a4c4c49, 20311bd5e7bSLukasz Majewski .p0_mpwrdlctl = 0x3f3f3133, 20411bd5e7bSLukasz Majewski .p1_mpwrdlctl = 0x39373f2e, 20511bd5e7bSLukasz Majewski }; 20611bd5e7bSLukasz Majewski 20711bd5e7bSLukasz Majewski static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = { 20811bd5e7bSLukasz Majewski .p0_mpwldectrl0 = 0x0040003c, 20911bd5e7bSLukasz Majewski .p0_mpwldectrl1 = 0x0032003e, 21011bd5e7bSLukasz Majewski .p0_mpdgctrl0 = 0x42350231, 21111bd5e7bSLukasz Majewski .p0_mpdgctrl1 = 0x021a0218, 21211bd5e7bSLukasz Majewski .p0_mprddlctl = 0x4b4b4e49, 21311bd5e7bSLukasz Majewski .p0_mpwrdlctl = 0x3f3f3035, 21411bd5e7bSLukasz Majewski }; 21511bd5e7bSLukasz Majewski 21611bd5e7bSLukasz Majewski /* DDR 64bit 1GB */ 21711bd5e7bSLukasz Majewski static struct mx6_ddr_sysinfo mem_dl = { 21811bd5e7bSLukasz Majewski .dsize = 2, 21911bd5e7bSLukasz Majewski .cs1_mirror = 0, 22011bd5e7bSLukasz Majewski /* config for full 4GB range so that get_mem_size() works */ 22111bd5e7bSLukasz Majewski .cs_density = 32, 22211bd5e7bSLukasz Majewski .ncs = 1, 22311bd5e7bSLukasz Majewski .bi_on = 1, 22411bd5e7bSLukasz Majewski .rtt_nom = 1, 22511bd5e7bSLukasz Majewski .rtt_wr = 0, 22611bd5e7bSLukasz Majewski .ralat = 5, 22711bd5e7bSLukasz Majewski .walat = 0, 22811bd5e7bSLukasz Majewski .mif3_mode = 3, 22911bd5e7bSLukasz Majewski .rst_to_cke = 0x23, 23011bd5e7bSLukasz Majewski .sde_to_rst = 0x10, 23111bd5e7bSLukasz Majewski }; 23211bd5e7bSLukasz Majewski 23311bd5e7bSLukasz Majewski /* DDR 32bit 512MB */ 23411bd5e7bSLukasz Majewski static struct mx6_ddr_sysinfo mem_s = { 23511bd5e7bSLukasz Majewski .dsize = 1, 23611bd5e7bSLukasz Majewski .cs1_mirror = 0, 23711bd5e7bSLukasz Majewski /* config for full 4GB range so that get_mem_size() works */ 23811bd5e7bSLukasz Majewski .cs_density = 32, 23911bd5e7bSLukasz Majewski .ncs = 1, 24011bd5e7bSLukasz Majewski .bi_on = 1, 24111bd5e7bSLukasz Majewski .rtt_nom = 1, 24211bd5e7bSLukasz Majewski .rtt_wr = 0, 24311bd5e7bSLukasz Majewski .ralat = 5, 24411bd5e7bSLukasz Majewski .walat = 0, 24511bd5e7bSLukasz Majewski .mif3_mode = 3, 24611bd5e7bSLukasz Majewski .rst_to_cke = 0x23, 24711bd5e7bSLukasz Majewski .sde_to_rst = 0x10, 24811bd5e7bSLukasz Majewski }; 24911bd5e7bSLukasz Majewski 25011bd5e7bSLukasz Majewski static void ccgr_init(void) 25111bd5e7bSLukasz Majewski { 25211bd5e7bSLukasz Majewski struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 25311bd5e7bSLukasz Majewski 25411bd5e7bSLukasz Majewski writel(0x00C03F3F, &ccm->CCGR0); 25511bd5e7bSLukasz Majewski writel(0x0030FC03, &ccm->CCGR1); 25611bd5e7bSLukasz Majewski writel(0x0FFFC000, &ccm->CCGR2); 25711bd5e7bSLukasz Majewski writel(0x3FF00000, &ccm->CCGR3); 25811bd5e7bSLukasz Majewski writel(0x00FFF300, &ccm->CCGR4); 25911bd5e7bSLukasz Majewski writel(0x0F0000C3, &ccm->CCGR5); 26011bd5e7bSLukasz Majewski writel(0x000003FF, &ccm->CCGR6); 26111bd5e7bSLukasz Majewski } 26211bd5e7bSLukasz Majewski 26311bd5e7bSLukasz Majewski static void gpr_init(void) 26411bd5e7bSLukasz Majewski { 26511bd5e7bSLukasz Majewski struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 26611bd5e7bSLukasz Majewski 26711bd5e7bSLukasz Majewski /* enable AXI cache for VDOA/VPU/IPU */ 26811bd5e7bSLukasz Majewski writel(0xF00000CF, &iomux->gpr[4]); 26911bd5e7bSLukasz Majewski /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ 27011bd5e7bSLukasz Majewski writel(0x007F007F, &iomux->gpr[6]); 27111bd5e7bSLukasz Majewski writel(0x007F007F, &iomux->gpr[7]); 27211bd5e7bSLukasz Majewski } 27311bd5e7bSLukasz Majewski 27411bd5e7bSLukasz Majewski static void spl_dram_init(void) 27511bd5e7bSLukasz Majewski { 27611bd5e7bSLukasz Majewski if (is_cpu_type(MXC_CPU_MX6SOLO)) { 27711bd5e7bSLukasz Majewski mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); 27811bd5e7bSLukasz Majewski mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr); 27911bd5e7bSLukasz Majewski } else if (is_cpu_type(MXC_CPU_MX6DL)) { 28011bd5e7bSLukasz Majewski mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); 28111bd5e7bSLukasz Majewski mx6_dram_cfg(&mem_dl, &mx6dl_1g_mmdc_calib, &h5tq2g63dfr); 28211bd5e7bSLukasz Majewski } else if (is_cpu_type(MXC_CPU_MX6Q)) { 28311bd5e7bSLukasz Majewski mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); 28411bd5e7bSLukasz Majewski mx6_dram_cfg(&mem_q, &mx6q_2g_mmdc_calib, &h5t04g63afr); 28511bd5e7bSLukasz Majewski } 28611bd5e7bSLukasz Majewski 28711bd5e7bSLukasz Majewski udelay(100); 28811bd5e7bSLukasz Majewski } 28911bd5e7bSLukasz Majewski 29011bd5e7bSLukasz Majewski void board_init_f(ulong dummy) 29111bd5e7bSLukasz Majewski { 29211bd5e7bSLukasz Majewski ccgr_init(); 29311bd5e7bSLukasz Majewski 29411bd5e7bSLukasz Majewski /* setup AIPS and disable watchdog */ 29511bd5e7bSLukasz Majewski arch_cpu_init(); 29611bd5e7bSLukasz Majewski 29711bd5e7bSLukasz Majewski gpr_init(); 29811bd5e7bSLukasz Majewski 29911bd5e7bSLukasz Majewski /* iomux */ 30011bd5e7bSLukasz Majewski board_early_init_f(); 30111bd5e7bSLukasz Majewski 30211bd5e7bSLukasz Majewski /* setup GP timer */ 30311bd5e7bSLukasz Majewski timer_init(); 30411bd5e7bSLukasz Majewski 30511bd5e7bSLukasz Majewski /* UART clocks enabled and gd valid - init serial console */ 30611bd5e7bSLukasz Majewski preloader_console_init(); 30711bd5e7bSLukasz Majewski 30811bd5e7bSLukasz Majewski /* DDR initialization */ 30911bd5e7bSLukasz Majewski spl_dram_init(); 31011bd5e7bSLukasz Majewski 31111bd5e7bSLukasz Majewski /* Clear the BSS. */ 31211bd5e7bSLukasz Majewski memset(__bss_start, 0, __bss_end - __bss_start); 31311bd5e7bSLukasz Majewski 31411bd5e7bSLukasz Majewski /* load/boot image from boot device */ 31511bd5e7bSLukasz Majewski board_init_r(NULL, 0); 31611bd5e7bSLukasz Majewski } 31711bd5e7bSLukasz Majewski #endif 318