1 /*
2  * Copyright (C) 2016-2017
3  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #include <common.h>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/iomux.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <asm/arch/sys_proto.h>
14 #include <asm/gpio.h>
15 #include <asm/mach-imx/iomux-v3.h>
16 #include <asm/mach-imx/mxc_i2c.h>
17 #include <asm/mach-imx/spi.h>
18 #include <asm/mach-imx/boot_mode.h>
19 #include <asm/io.h>
20 #include <fsl_esdhc.h>
21 #include <mmc.h>
22 #include <netdev.h>
23 #include <micrel.h>
24 #include <phy.h>
25 #include <input.h>
26 #include <i2c.h>
27 #include <spl.h>
28 
29 DECLARE_GLOBAL_DATA_PTR;
30 
31 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
32 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
33 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
34 
35 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
36 	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
37 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
38 
39 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
40 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
41 
42 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |		\
43 	PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
44 
45 #define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
46 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
47 	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
48 
49 #define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |          \
50 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
51 	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
52 
53 #define USDHC2_CD_GPIO		IMX_GPIO_NR(1, 4)
54 #define ETH_PHY_RESET		IMX_GPIO_NR(1, 27)
55 #define ECSPI3_CS0		IMX_GPIO_NR(4, 24)
56 #define ECSPI3_FLWP		IMX_GPIO_NR(4, 27)
57 #define NOR_WP			IMX_GPIO_NR(1, 1)
58 #define DISPLAY_EN		IMX_GPIO_NR(1, 2)
59 
60 int dram_init(void)
61 {
62 	gd->ram_size = imx_ddr_size();
63 
64 	return 0;
65 }
66 
67 static iomux_v3_cfg_t const uart1_pads[] = {
68 	IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
69 	IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
70 };
71 
72 static iomux_v3_cfg_t const usdhc2_pads[] = {
73 	IOMUX_PADS(PAD_SD2_CLK__SD2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
74 	IOMUX_PADS(PAD_SD2_CMD__SD2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
75 	IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
76 	IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
77 	IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
78 	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
79 	/* Carrier MicroSD Card Detect */
80 	IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04  | MUX_PAD_CTRL(NO_PAD_CTRL)),
81 };
82 
83 static iomux_v3_cfg_t const usdhc3_pads[] = {
84 	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
85 	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
86 	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
87 	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
88 	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
89 	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
90 	IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
91 	IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
92 	IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
93 	IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
94 	IOMUX_PADS(PAD_SD3_RST__SD3_RESET  | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
95 };
96 
97 static iomux_v3_cfg_t const enet_pads[] = {
98 	IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
99 	IOMUX_PADS(PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
100 	IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
101 	IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
102 	IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
103 	IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
104 	IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
105 	IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL
106 		   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
107 	IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK
108 		   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
109 	IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
110 	IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
111 	IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
112 	IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
113 	IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
114 	IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL
115 		   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
116 	/* KSZ9031 PHY Reset */
117 	IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27  | MUX_PAD_CTRL(NO_PAD_CTRL)),
118 };
119 
120 static void setup_iomux_uart(void)
121 {
122 	SETUP_IOMUX_PADS(uart1_pads);
123 }
124 
125 static void setup_iomux_enet(void)
126 {
127 	SETUP_IOMUX_PADS(enet_pads);
128 
129 	/* Reset KSZ9031 PHY */
130 	gpio_direction_output(ETH_PHY_RESET, 0);
131 	mdelay(10);
132 	gpio_set_value(ETH_PHY_RESET, 1);
133 	udelay(100);
134 }
135 
136 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
137 	{USDHC3_BASE_ADDR},
138 	{USDHC2_BASE_ADDR},
139 };
140 
141 int board_mmc_getcd(struct mmc *mmc)
142 {
143 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
144 	int ret = 0;
145 
146 	switch (cfg->esdhc_base) {
147 	case USDHC2_BASE_ADDR:
148 		ret = !gpio_get_value(USDHC2_CD_GPIO);
149 		break;
150 	case USDHC3_BASE_ADDR:
151 		/*
152 		 * eMMC don't have card detect pin - since it is soldered to the
153 		 * PCB board
154 		 */
155 		ret = 1;
156 		break;
157 	}
158 	return ret;
159 }
160 
161 int board_mmc_init(bd_t *bis)
162 {
163 	int ret;
164 	u32 index = 0;
165 
166 	/*
167 	 * MMC MAP
168 	 * (U-Boot device node)    (Physical Port)
169 	 * mmc0                    Soldered on board eMMC device
170 	 * mmc1                    MicroSD card
171 	 */
172 	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
173 		switch (index) {
174 		case 0:
175 			SETUP_IOMUX_PADS(usdhc3_pads);
176 			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
177 			usdhc_cfg[0].max_bus_width = 8;
178 			break;
179 		case 1:
180 			SETUP_IOMUX_PADS(usdhc2_pads);
181 			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
182 			usdhc_cfg[1].max_bus_width = 4;
183 			gpio_direction_input(USDHC2_CD_GPIO);
184 			break;
185 		default:
186 			printf("Warning: More USDHC controllers (%d) than supported (%d)\n",
187 			       index + 1, CONFIG_SYS_FSL_USDHC_NUM);
188 			return -EINVAL;
189 		}
190 
191 		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
192 		if (ret)
193 			return ret;
194 	}
195 
196 	return 0;
197 }
198 
199 static iomux_v3_cfg_t const eimnor_pads[] = {
200 	IOMUX_PADS(PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
201 	IOMUX_PADS(PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
202 	IOMUX_PADS(PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
203 	IOMUX_PADS(PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
204 	IOMUX_PADS(PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
205 	IOMUX_PADS(PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
206 	IOMUX_PADS(PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
207 	IOMUX_PADS(PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
208 	IOMUX_PADS(PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
209 	IOMUX_PADS(PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
210 	IOMUX_PADS(PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
211 	IOMUX_PADS(PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
212 	IOMUX_PADS(PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
213 	IOMUX_PADS(PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
214 	IOMUX_PADS(PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
215 	IOMUX_PADS(PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
216 	IOMUX_PADS(PAD_EIM_DA0__EIM_AD00   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
217 	IOMUX_PADS(PAD_EIM_DA1__EIM_AD01   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
218 	IOMUX_PADS(PAD_EIM_DA2__EIM_AD02   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
219 	IOMUX_PADS(PAD_EIM_DA3__EIM_AD03   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
220 	IOMUX_PADS(PAD_EIM_DA4__EIM_AD04   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
221 	IOMUX_PADS(PAD_EIM_DA5__EIM_AD05   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
222 	IOMUX_PADS(PAD_EIM_DA6__EIM_AD06   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
223 	IOMUX_PADS(PAD_EIM_DA7__EIM_AD07   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
224 	IOMUX_PADS(PAD_EIM_DA8__EIM_AD08   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
225 	IOMUX_PADS(PAD_EIM_DA9__EIM_AD09   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
226 	IOMUX_PADS(PAD_EIM_DA10__EIM_AD10  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
227 	IOMUX_PADS(PAD_EIM_DA11__EIM_AD11  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
228 	IOMUX_PADS(PAD_EIM_DA12__EIM_AD12  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
229 	IOMUX_PADS(PAD_EIM_DA13__EIM_AD13  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
230 	IOMUX_PADS(PAD_EIM_DA14__EIM_AD14  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
231 	IOMUX_PADS(PAD_EIM_DA15__EIM_AD15  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
232 	IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
233 	IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
234 	IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
235 	IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
236 	IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
237 	IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
238 	IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
239 	IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
240 	IOMUX_PADS(PAD_EIM_A24__EIM_ADDR24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
241 	IOMUX_PADS(PAD_EIM_A25__EIM_ADDR25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
242 	IOMUX_PADS(PAD_EIM_OE__EIM_OE_B	| MUX_PAD_CTRL(NO_PAD_CTRL)),
243 	IOMUX_PADS(PAD_EIM_RW__EIM_RW		| MUX_PAD_CTRL(NO_PAD_CTRL)),
244 	IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B	| MUX_PAD_CTRL(NO_PAD_CTRL)),
245 	IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01	| MUX_PAD_CTRL(NO_PAD_CTRL)),
246 };
247 
248 static void eimnor_cs_setup(void)
249 {
250 	struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
251 
252 
253 	/* NOR configuration */
254 	writel(0x00620181, &weim_regs->cs0gcr1);
255 	writel(0x00000001, &weim_regs->cs0gcr2);
256 	writel(0x0b020000, &weim_regs->cs0rcr1);
257 	writel(0x0000b000, &weim_regs->cs0rcr2);
258 	writel(0x0804a240, &weim_regs->cs0wcr1);
259 	writel(0x00000000, &weim_regs->cs0wcr2);
260 
261 	writel(0x00000120, &weim_regs->wcr);
262 	writel(0x00000010, &weim_regs->wiar);
263 	writel(0x00000000, &weim_regs->ear);
264 
265 	set_chipselect_size(CS0_128);
266 }
267 
268 static void setup_eimnor(void)
269 {
270 	SETUP_IOMUX_PADS(eimnor_pads);
271 	gpio_direction_output(NOR_WP, 1);
272 
273 	enable_eim_clk(1);
274 	eimnor_cs_setup();
275 }
276 
277 /* mccmon6 board has SPI Flash is connected to SPI3 */
278 int board_spi_cs_gpio(unsigned bus, unsigned cs)
279 {
280 	return (bus == 2 && cs == 0) ? ECSPI3_CS0 : -1;
281 }
282 
283 static iomux_v3_cfg_t const ecspi3_pads[] = {
284 	/* SPI3 */
285 	IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
286 	IOMUX_PADS(PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
287 	IOMUX_PADS(PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
288 	IOMUX_PADS(PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
289 };
290 
291 void setup_spi(void)
292 {
293 	SETUP_IOMUX_PADS(ecspi3_pads);
294 
295 	enable_spi_clk(true, 2);
296 
297 	/* set cs0 to high */
298 	gpio_direction_output(ECSPI3_CS0, 1);
299 
300 	/* set flwp to high */
301 	gpio_direction_output(ECSPI3_FLWP, 1);
302 }
303 
304 struct i2c_pads_info mx6q_i2c1_pad_info = {
305 	.scl = {
306 		.i2c_mode = MX6Q_PAD_CSI0_DAT9__I2C1_SCL
307 			| MUX_PAD_CTRL(I2C_PAD_CTRL),
308 		.gpio_mode = MX6Q_PAD_CSI0_DAT9__GPIO5_IO27
309 			| MUX_PAD_CTRL(I2C_PAD_CTRL),
310 		.gp = IMX_GPIO_NR(5, 27)
311 	},
312 	.sda = {
313 		.i2c_mode = MX6Q_PAD_CSI0_DAT8__I2C1_SDA
314 			| MUX_PAD_CTRL(I2C_PAD_CTRL),
315 		.gpio_mode = MX6Q_PAD_CSI0_DAT8__GPIO5_IO26
316 			| MUX_PAD_CTRL(I2C_PAD_CTRL),
317 		.gp = IMX_GPIO_NR(5, 26)
318 	}
319 };
320 
321 struct i2c_pads_info mx6q_i2c2_pad_info = {
322 	.scl = {
323 		.i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
324 			| MUX_PAD_CTRL(I2C_PAD_CTRL),
325 		.gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
326 			| MUX_PAD_CTRL(I2C_PAD_CTRL),
327 		.gp = IMX_GPIO_NR(4, 12)
328 	},
329 	.sda = {
330 		.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
331 			| MUX_PAD_CTRL(I2C_PAD_CTRL),
332 		.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
333 			| MUX_PAD_CTRL(I2C_PAD_CTRL),
334 		.gp = IMX_GPIO_NR(4, 13)
335 	}
336 };
337 
338 int board_eth_init(bd_t *bis)
339 {
340 	setup_iomux_enet();
341 
342 	return cpu_eth_init(bis);
343 }
344 
345 int board_early_init_f(void)
346 {
347 	setup_iomux_uart();
348 
349 	return 0;
350 }
351 
352 int board_init(void)
353 {
354 	/* address of boot parameters */
355 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
356 
357 	gpio_direction_output(DISPLAY_EN, 1);
358 
359 	setup_eimnor();
360 	setup_spi();
361 
362 	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c1_pad_info);
363 	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
364 
365 	return 0;
366 }
367 
368 int board_late_init(void)
369 {
370 	setenv("board_name", "mccmon6");
371 
372 	return 0;
373 }
374 
375 int checkboard(void)
376 {
377 	puts("Board: MCCMON6\n");
378 
379 	return 0;
380 }
381 
382 int board_phy_config(struct phy_device *phydev)
383 {
384 	/*
385 	 * Default setting for GMII Clock Pad Skew Register 0x1EF:
386 	 * MMD Address 0x2h, Register 0x8h
387 	 *
388 	 * GTX_CLK Pad Skew 0xF -> 0.9 nsec skew
389 	 * RX_CLK Pad Skew 0xF -> 0.9 nsec skew
390 	 *
391 	 * Adjustment -> write 0x3FF:
392 	 * GTX_CLK Pad Skew 0x1F -> 1.8 nsec skew
393 	 * RX_CLK Pad Skew 0x1F -> 1.8 nsec skew
394 	 *
395 	 */
396 	ksz9031_phy_extended_write(phydev, 0x2,
397 				   MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
398 				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x3FF);
399 
400 	ksz9031_phy_extended_write(phydev, 0x02,
401 				   MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
402 				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x00FF);
403 
404 	ksz9031_phy_extended_write(phydev, 0x2,
405 				   MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
406 				   MII_KSZ9031_MOD_DATA_NO_POST_INC,
407 				   0x3333);
408 
409 	ksz9031_phy_extended_write(phydev, 0x2,
410 				   MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
411 				   MII_KSZ9031_MOD_DATA_NO_POST_INC,
412 				   0x2052);
413 
414 	if (phydev->drv->config)
415 		phydev->drv->config(phydev);
416 
417 	return 0;
418 }
419 
420 #ifdef CONFIG_SPL_BOARD_INIT
421 void spl_board_init(void)
422 {
423 	setup_eimnor();
424 
425 	gpio_direction_output(DISPLAY_EN, 1);
426 }
427 #endif /* CONFIG_SPL_BOARD_INIT */
428 
429 #ifdef CONFIG_SPL_BUILD
430 void board_boot_order(u32 *spl_boot_list)
431 {
432 	switch (spl_boot_device()) {
433 	case BOOT_DEVICE_MMC2:
434 	case BOOT_DEVICE_MMC1:
435 		spl_boot_list[0] = BOOT_DEVICE_MMC2;
436 		spl_boot_list[1] = BOOT_DEVICE_MMC1;
437 		break;
438 
439 	case BOOT_DEVICE_NOR:
440 		spl_boot_list[0] = BOOT_DEVICE_NOR;
441 		break;
442 	}
443 }
444 #endif /* CONFIG_SPL_BUILD */
445 
446 #ifdef CONFIG_SPL_OS_BOOT
447 int spl_start_uboot(void)
448 {
449 	char s[16];
450 	int ret;
451 	/*
452 	 * We use BOOT_DEVICE_MMC1, but SD card is connected
453 	 * to MMC2
454 	 *
455 	 * Correct "mapping" is delivered in board defined
456 	 * board_boot_order() function.
457 	 *
458 	 * SD card boot is regarded as a "development" one,
459 	 * hence we _always_ go through the u-boot.
460 	 *
461 	 */
462 	if (spl_boot_device() == BOOT_DEVICE_MMC1)
463 		return 1;
464 
465 	/* break into full u-boot on 'c' */
466 	if (serial_tstc() && serial_getc() == 'c')
467 		return 1;
468 
469 	env_init();
470 	ret = getenv_f("boot_os", s, sizeof(s));
471 	if ((ret != -1) && (strcmp(s, "no") == 0))
472 		return 1;
473 
474 	/*
475 	 * Check if SWUpdate recovery needs to be started
476 	 *
477 	 * recovery_status = NULL (not set - ret == -1) -> normal operation
478 	 *
479 	 * recovery_status = progress or
480 	 * recovery_status = failed   or
481 	 * recovery_status = <any value> -> start SWUpdate
482 	 *
483 	 */
484 	ret = getenv_f("recovery_status", s, sizeof(s));
485 	if (ret != -1)
486 		return 1;
487 
488 	return 0;
489 }
490 #endif /* CONFIG_SPL_OS_BOOT */
491