1 /* 2 * Copyright (C) 2017 DENX Software Engineering 3 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <spl.h> 10 #include <libfdt.h> 11 #include <asm/io.h> 12 #include <asm/arch/clock.h> 13 #include <asm/arch/mx6-ddr.h> 14 #include <asm/arch/mx6-pins.h> 15 #include "asm/arch/crm_regs.h" 16 #include <asm/arch/sys_proto.h> 17 #include <asm/arch/imx-regs.h> 18 #include "asm/arch/iomux.h" 19 #include <asm/mach-imx/iomux-v3.h> 20 #include <environment.h> 21 #include <fsl_esdhc.h> 22 #include <netdev.h> 23 #include "common.h" 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { 28 .dram_sdclk_0 = 0x00000030, 29 .dram_sdclk_1 = 0x00000030, 30 .dram_cas = 0x00000030, 31 .dram_ras = 0x00000030, 32 .dram_reset = 0x00000030, 33 .dram_sdcke0 = 0x00003000, 34 .dram_sdcke1 = 0x00003000, 35 .dram_sdba2 = 0x00000000, 36 .dram_sdodt0 = 0x00000030, 37 .dram_sdodt1 = 0x00000030, 38 39 .dram_sdqs0 = 0x00000030, 40 .dram_sdqs1 = 0x00000030, 41 .dram_sdqs2 = 0x00000030, 42 .dram_sdqs3 = 0x00000030, 43 .dram_sdqs4 = 0x00000030, 44 .dram_sdqs5 = 0x00000030, 45 .dram_sdqs6 = 0x00000030, 46 .dram_sdqs7 = 0x00000030, 47 48 .dram_dqm0 = 0x00000030, 49 .dram_dqm1 = 0x00000030, 50 .dram_dqm2 = 0x00000030, 51 .dram_dqm3 = 0x00000030, 52 .dram_dqm4 = 0x00000030, 53 .dram_dqm5 = 0x00000030, 54 .dram_dqm6 = 0x00000030, 55 .dram_dqm7 = 0x00000030, 56 }; 57 58 static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { 59 .grp_ddr_type = 0x000c0000, 60 .grp_ddrmode_ctl = 0x00020000, 61 .grp_ddrpke = 0x00000000, 62 .grp_addds = 0x00000030, 63 .grp_ctlds = 0x00000030, 64 .grp_ddrmode = 0x00020000, 65 .grp_b0ds = 0x00000030, 66 .grp_b1ds = 0x00000030, 67 .grp_b2ds = 0x00000030, 68 .grp_b3ds = 0x00000030, 69 .grp_b4ds = 0x00000030, 70 .grp_b5ds = 0x00000030, 71 .grp_b6ds = 0x00000030, 72 .grp_b7ds = 0x00000030, 73 }; 74 75 /* 4x128Mx16.cfg */ 76 static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = { 77 .p0_mpwldectrl0 = 0x002D0028, 78 .p0_mpwldectrl1 = 0x0032002D, 79 .p1_mpwldectrl0 = 0x00210036, 80 .p1_mpwldectrl1 = 0x0019002E, 81 .p0_mpdgctrl0 = 0x4349035C, 82 .p0_mpdgctrl1 = 0x0348033D, 83 .p1_mpdgctrl0 = 0x43550362, 84 .p1_mpdgctrl1 = 0x03520316, 85 .p0_mprddlctl = 0x41393940, 86 .p1_mprddlctl = 0x3F3A3C47, 87 .p0_mpwrdlctl = 0x413A423A, 88 .p1_mpwrdlctl = 0x4042483E, 89 }; 90 91 /* MT41K128M16JT-125 (2Gb density) */ 92 static const struct mx6_ddr3_cfg mt41k128m16jt_125 = { 93 .mem_speed = 1600, 94 .density = 2, 95 .width = 16, 96 .banks = 8, 97 .rowaddr = 14, 98 .coladdr = 10, 99 .pagesz = 2, 100 .trcd = 1375, 101 .trcmin = 4875, 102 .trasmin = 3500, 103 }; 104 105 static void ccgr_init(void) 106 { 107 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 108 109 writel(0x00C03F3F, &ccm->CCGR0); 110 writel(0x0030FC3F, &ccm->CCGR1); 111 writel(0x0FFFCFC0, &ccm->CCGR2); 112 writel(0x3FF00000, &ccm->CCGR3); 113 writel(0x00FFF300, &ccm->CCGR4); 114 writel(0x0F0000C3, &ccm->CCGR5); 115 writel(0x000003FF, &ccm->CCGR6); 116 } 117 118 static void spl_dram_init(void) 119 { 120 struct mx6_ddr_sysinfo sysinfo = { 121 /* width of data bus:0=16,1=32,2=64 */ 122 .dsize = 2, 123 /* config for full 4GB range so that get_mem_size() works */ 124 .cs_density = 32, /* 32Gb per CS */ 125 /* single chip select */ 126 .ncs = 1, 127 .cs1_mirror = 0, 128 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ 129 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ 130 .walat = 1, /* Write additional latency */ 131 .ralat = 5, /* Read additional latency */ 132 .mif3_mode = 3, /* Command prediction working mode */ 133 .bi_on = 1, /* Bank interleaving enabled */ 134 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 135 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 136 .pd_fast_exit = 1, /* enable precharge power-down fast exit */ 137 .ddr_type = DDR_TYPE_DDR3, 138 .refsel = 1, /* Refresh cycles at 32KHz */ 139 .refr = 7, /* 8 refresh commands per refresh cycle */ 140 }; 141 142 mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); 143 mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k128m16jt_125); 144 } 145 146 #ifdef CONFIG_SPL_SPI_SUPPORT 147 static void displ5_init_ecspi(void) 148 { 149 displ5_set_iomux_ecspi_spl(); 150 enable_spi_clk(1, 1); 151 } 152 #else 153 static inline void displ5_init_ecspi(void) { } 154 #endif 155 156 #ifdef CONFIG_SPL_MMC_SUPPORT 157 static struct fsl_esdhc_cfg usdhc_cfg = { 158 .esdhc_base = USDHC4_BASE_ADDR, 159 .max_bus_width = 8, 160 }; 161 162 int board_mmc_init(bd_t *bd) 163 { 164 displ5_set_iomux_usdhc_spl(); 165 166 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 167 gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk; 168 169 return fsl_esdhc_initialize(bd, &usdhc_cfg); 170 } 171 #endif 172 173 void board_init_f(ulong dummy) 174 { 175 ccgr_init(); 176 177 arch_cpu_init(); 178 179 gpr_init(); 180 181 /* setup GP timer */ 182 timer_init(); 183 184 displ5_set_iomux_uart_spl(); 185 186 /* UART clocks enabled and gd valid - init serial console */ 187 preloader_console_init(); 188 189 displ5_init_ecspi(); 190 191 /* DDR initialization */ 192 spl_dram_init(); 193 194 /* Clear the BSS. */ 195 memset(__bss_start, 0, __bss_end - __bss_start); 196 197 /* load/boot image from boot device */ 198 board_init_r(NULL, 0); 199 } 200 201 void board_boot_order(u32 *spl_boot_list) 202 { 203 /* Default boot sequence SPI -> MMC */ 204 spl_boot_list[0] = spl_boot_device(); 205 spl_boot_list[1] = BOOT_DEVICE_MMC1; 206 spl_boot_list[2] = BOOT_DEVICE_UART; 207 spl_boot_list[3] = BOOT_DEVICE_NONE; 208 209 #ifdef CONFIG_SPL_ENV_SUPPORT 210 /* 'fastboot' */ 211 const char *s; 212 213 env_init(); 214 env_load(); 215 216 s = env_get("BOOT_FROM"); 217 if (s && strcmp(s, "ACTIVE") == 0) { 218 spl_boot_list[0] = BOOT_DEVICE_MMC1; 219 spl_boot_list[1] = spl_boot_device(); 220 } 221 #endif 222 } 223 224 void reset_cpu(ulong addr) {} 225 226 #ifdef CONFIG_SPL_LOAD_FIT 227 int board_fit_config_name_match(const char *name) 228 { 229 return 0; 230 } 231 #endif 232 233 #ifdef CONFIG_SPL_OS_BOOT 234 /* Return: 1 - boot to U-Boot. 0 - boot OS (falcon mode) */ 235 int spl_start_uboot(void) 236 { 237 /* break into full u-boot on 'c' */ 238 if (serial_tstc() && serial_getc() == 'c') 239 return 1; 240 241 #ifdef CONFIG_SPL_ENV_SUPPORT 242 if (env_get_yesno("boot_os") != 1) 243 return 1; 244 #endif 245 return 0; 246 } 247 #endif 248