1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2017 DENX Software Engineering 4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <asm/io.h> 10 #include <asm/arch/clock.h> 11 #include <asm/arch/imx-regs.h> 12 #include <asm/arch/iomux.h> 13 #include <asm/arch/mx6-pins.h> 14 #include <asm/arch/mx6-ddr.h> 15 #include <asm/arch/sys_proto.h> 16 #include <errno.h> 17 #include <asm/gpio.h> 18 #include <malloc.h> 19 #include <asm/mach-imx/iomux-v3.h> 20 #include <asm/mach-imx/mxc_i2c.h> 21 #include <asm/mach-imx/boot_mode.h> 22 #include <asm/mach-imx/spi.h> 23 #include <mmc.h> 24 #include <fsl_esdhc.h> 25 #include <miiphy.h> 26 #include <netdev.h> 27 #include <i2c.h> 28 29 #include <dm.h> 30 #include <dm/platform_data/serial_mxc.h> 31 #include <dm/platdata.h> 32 33 #ifndef CONFIG_MXC_SPI 34 #error "CONFIG_SPI must be set for this board" 35 #error "Please check your config file" 36 #endif 37 38 #include "common.h" 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 static bool hw_ids_valid; 43 static bool sw_ids_valid; 44 static u32 cpu_id; 45 static u32 unit_id; 46 47 #define EM_PAD IMX_GPIO_NR(3, 29) 48 #define SW0 IMX_GPIO_NR(2, 4) 49 #define SW1 IMX_GPIO_NR(2, 5) 50 #define SW2 IMX_GPIO_NR(2, 6) 51 #define SW3 IMX_GPIO_NR(2, 7) 52 #define HW0 IMX_GPIO_NR(6, 7) 53 #define HW1 IMX_GPIO_NR(6, 9) 54 #define HW2 IMX_GPIO_NR(6, 10) 55 #define HW3 IMX_GPIO_NR(6, 11) 56 #define HW4 IMX_GPIO_NR(4, 7) 57 #define HW5 IMX_GPIO_NR(4, 11) 58 #define HW6 IMX_GPIO_NR(4, 13) 59 #define HW7 IMX_GPIO_NR(4, 15) 60 61 int gpio_table_sw_ids[] = { 62 SW0, SW1, SW2, SW3 63 }; 64 65 const char *gpio_table_sw_ids_names[] = { 66 "sw0", "sw1", "sw2", "sw3" 67 }; 68 69 int gpio_table_hw_ids[] = { 70 HW0, HW1, HW2, HW3, HW4, HW5, HW6, HW7 71 }; 72 73 const char *gpio_table_hw_ids_names[] = { 74 "hw0", "hw1", "hw2", "hw3", "hw4", "hw5", "hw6", "hw7" 75 }; 76 77 static int get_board_id(int *ids, const char **c, int size, 78 bool *valid, u32 *id) 79 { 80 int i, ret, val; 81 82 *valid = false; 83 84 for (i = 0; i < size; i++) { 85 ret = gpio_request(ids[i], c[i]); 86 if (ret) { 87 printf("Can't request SWx gpios\n"); 88 return ret; 89 } 90 } 91 92 for (i = 0; i < size; i++) { 93 ret = gpio_direction_input(ids[i]); 94 if (ret) { 95 printf("Can't set SWx gpios direction\n"); 96 return ret; 97 } 98 } 99 100 for (i = 0; i < size; i++) { 101 val = gpio_get_value(ids[i]); 102 if (val < 0) { 103 printf("Can't get SW%d ID\n", i); 104 *id = 0; 105 return val; 106 } 107 *id |= val << i; 108 } 109 *valid = true; 110 111 return 0; 112 } 113 114 int dram_init(void) 115 { 116 gd->ram_size = imx_ddr_size(); 117 118 return 0; 119 } 120 121 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 122 /* I2C1: TFA9879 */ 123 struct i2c_pads_info i2c_pad_info0 = { 124 .scl = { 125 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, 126 .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC, 127 .gp = IMX_GPIO_NR(3, 21) 128 }, 129 .sda = { 130 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, 131 .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC, 132 .gp = IMX_GPIO_NR(3, 28) 133 } 134 }; 135 136 /* I2C2: TIVO TM4C123 */ 137 struct i2c_pads_info i2c_pad_info1 = { 138 .scl = { 139 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC, 140 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, 141 .gp = IMX_GPIO_NR(2, 30) 142 }, 143 .sda = { 144 .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC, 145 .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC, 146 .gp = IMX_GPIO_NR(3, 16) 147 } 148 }; 149 150 /* I2C3: PMIC PF0100, EEPROM AT24C256C */ 151 struct i2c_pads_info i2c_pad_info2 = { 152 .scl = { 153 .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC, 154 .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC, 155 .gp = IMX_GPIO_NR(3, 17) 156 }, 157 .sda = { 158 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, 159 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, 160 .gp = IMX_GPIO_NR(3, 18) 161 } 162 }; 163 164 iomux_v3_cfg_t const misc_pads[] = { 165 /* Prod ID GPIO pins */ 166 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), 167 MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), 168 MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), 169 MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), 170 171 /* HW revision GPIO pins */ 172 MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), 173 MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), 174 MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), 175 MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), 176 MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), 177 MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), 178 MX6_PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), 179 MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), 180 181 /* XTALOSC */ 182 MX6_PAD_GPIO_3__XTALOSC_REF_CLK_24M | MUX_PAD_CTRL(NO_PAD_CTRL), 183 184 /* Emergency recovery pin */ 185 MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), 186 }; 187 188 #ifdef CONFIG_FSL_ESDHC 189 struct fsl_esdhc_cfg usdhc_cfg[1] = { 190 { USDHC4_BASE_ADDR, 0, 8, }, 191 }; 192 193 int board_mmc_getcd(struct mmc *mmc) 194 { 195 return 1; 196 } 197 198 int board_mmc_init(bd_t *bis) 199 { 200 displ5_set_iomux_usdhc(); 201 202 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 203 204 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); 205 } 206 #endif /* CONFIG_FSL_ESDHC */ 207 208 static void displ5_setup_ecspi(void) 209 { 210 int ret; 211 212 displ5_set_iomux_ecspi(); 213 214 ret = gpio_request(IMX_GPIO_NR(5, 29), "spi2_cs0"); 215 if (!ret) 216 gpio_direction_output(IMX_GPIO_NR(5, 29), 1); 217 218 ret = gpio_request(IMX_GPIO_NR(7, 0), "spi2_#wp"); 219 if (!ret) 220 gpio_direction_output(IMX_GPIO_NR(7, 0), 1); 221 } 222 223 #ifdef CONFIG_FEC_MXC 224 iomux_v3_cfg_t const enet_pads[] = { 225 MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN | MUX_PAD_CTRL(ENET_PAD_CTRL), 226 MX6_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL), 227 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 228 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 229 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 230 231 /* for old evalboard with R159 present and R160 not populated */ 232 MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL), 233 234 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 235 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 236 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 237 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 238 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 239 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 240 241 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 242 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 243 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 244 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 245 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 246 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 247 /*INT#_GBE*/ 248 MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), 249 }; 250 251 static void setup_iomux_enet(void) 252 { 253 SETUP_IOMUX_PADS(enet_pads); 254 gpio_direction_input(IMX_GPIO_NR(1, 28)); /*INT#_GBE*/ 255 } 256 257 static int setup_mac_from_fuse(void) 258 { 259 unsigned char enetaddr[6]; 260 int ret; 261 262 ret = eth_env_get_enetaddr("ethaddr", enetaddr); 263 if (ret) /* ethaddr is already set */ 264 return 0; 265 266 imx_get_mac_from_fuse(0, enetaddr); 267 268 if (is_valid_ethaddr(enetaddr)) { 269 eth_env_set_enetaddr("ethaddr", enetaddr); 270 return 0; 271 } 272 273 return 0; 274 } 275 276 int board_eth_init(bd_t *bd) 277 { 278 struct phy_device *phydev; 279 struct mii_dev *bus; 280 int ret; 281 282 setup_iomux_enet(); 283 284 iomuxc_set_rgmii_io_voltage(DDR_SEL_1P5V_IO); 285 286 ret = enable_fec_anatop_clock(0, ENET_125MHZ); 287 if (ret) 288 return ret; 289 290 setup_mac_from_fuse(); 291 292 bus = fec_get_miibus(IMX_FEC_BASE, -1); 293 if (!bus) 294 return -ENODEV; 295 296 /* 297 * We use here the "rgmii-id" mode of operation and allow M88E1512 298 * PHY to use its internally callibrated RX/TX delays 299 */ 300 phydev = phy_find_by_mask(bus, 0xffffffff /* (0xf << 4) */, 301 PHY_INTERFACE_MODE_RGMII_ID); 302 if (!phydev) { 303 ret = -ENODEV; 304 goto err_phy; 305 } 306 307 /* display5 due to PCB routing can only work with 100 Mbps */ 308 phydev->advertising &= ~(ADVERTISED_1000baseX_Half | 309 ADVERTISED_1000baseX_Full | 310 SUPPORTED_1000baseT_Half | 311 SUPPORTED_1000baseT_Full); 312 313 ret = fec_probe(bd, -1, IMX_FEC_BASE, bus, phydev); 314 if (ret) 315 goto err_sw; 316 317 return 0; 318 319 err_sw: 320 free(phydev); 321 err_phy: 322 mdio_unregister(bus); 323 free(bus); 324 return ret; 325 } 326 #endif /* CONFIG_FEC_MXC */ 327 328 /* 329 * Do not overwrite the console 330 * Always use serial for U-Boot console 331 */ 332 int overwrite_console(void) 333 { 334 return 1; 335 } 336 337 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) 338 int ft_board_setup(void *blob, bd_t *bd) 339 { 340 fdt_fixup_ethernet(blob); 341 return 0; 342 } 343 #endif 344 345 int board_init(void) 346 { 347 debug("board init\n"); 348 /* address of boot parameters */ 349 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 350 351 /* Setup iomux for non console UARTS */ 352 displ5_set_iomux_uart(); 353 354 displ5_setup_ecspi(); 355 356 SETUP_IOMUX_PADS(misc_pads); 357 358 get_board_id(gpio_table_sw_ids, &gpio_table_sw_ids_names[0], 359 ARRAY_SIZE(gpio_table_sw_ids), &sw_ids_valid, &unit_id); 360 debug("SWx unit_id 0x%x\n", unit_id); 361 362 get_board_id(gpio_table_hw_ids, &gpio_table_hw_ids_names[0], 363 ARRAY_SIZE(gpio_table_hw_ids), &hw_ids_valid, &cpu_id); 364 debug("HWx cpu_id 0x%x\n", cpu_id); 365 366 if (hw_ids_valid && sw_ids_valid) 367 printf("ID: unit type 0x%x rev 0x%x\n", unit_id, cpu_id); 368 369 udelay(25); 370 371 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); 372 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 373 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); 374 375 return 0; 376 } 377 378 #ifdef CONFIG_CMD_BMODE 379 static const struct boot_mode board_boot_modes[] = { 380 /* eMMC, USDHC-4, 8-bit bus width */ 381 /* SPI-NOR, ECSPI-2 SS0, 3-bytes addressing */ 382 {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)}, 383 {"spinor", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x09)}, 384 {NULL, 0}, 385 }; 386 387 static void setup_boot_modes(void) 388 { 389 add_board_boot_modes(board_boot_modes); 390 } 391 #else 392 static inline void setup_boot_modes(void) {} 393 #endif 394 395 int misc_init_r(void) 396 { 397 int ret; 398 399 setup_boot_modes(); 400 401 ret = gpio_request(EM_PAD, "Emergency_PAD"); 402 if (ret) { 403 printf("Can't request emergency PAD gpio\n"); 404 return ret; 405 } 406 407 ret = gpio_direction_input(EM_PAD); 408 if (ret) { 409 printf("Can't set emergency PAD direction\n"); 410 return ret; 411 } 412 413 return 0; 414 } 415 416 static struct mxc_serial_platdata mxc_serial_plat = { 417 .reg = (struct mxc_uart *)UART5_BASE, 418 }; 419 420 U_BOOT_DEVICE(mxc_serial) = { 421 .name = "serial_mxc", 422 .platdata = &mxc_serial_plat, 423 }; 424