1 /* 2 * Copyright (C) 2017 DENX Software Engineering 3 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <asm/io.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/imx-regs.h> 13 #include <asm/arch/iomux.h> 14 #include <asm/arch/mx6-pins.h> 15 #include <asm/arch/mx6-ddr.h> 16 #include <asm/arch/sys_proto.h> 17 #include <errno.h> 18 #include <asm/gpio.h> 19 #include <malloc.h> 20 #include <asm/mach-imx/iomux-v3.h> 21 #include <asm/mach-imx/mxc_i2c.h> 22 #include <asm/mach-imx/boot_mode.h> 23 #include <asm/mach-imx/spi.h> 24 #include <mmc.h> 25 #include <fsl_esdhc.h> 26 #include <miiphy.h> 27 #include <netdev.h> 28 #include <i2c.h> 29 30 #include <dm.h> 31 #include <dm/platform_data/serial_mxc.h> 32 #include <dm/platdata.h> 33 34 #ifndef CONFIG_MXC_SPI 35 #error "CONFIG_SPI must be set for this board" 36 #error "Please check your config file" 37 #endif 38 39 #include "common.h" 40 41 DECLARE_GLOBAL_DATA_PTR; 42 43 static bool hw_ids_valid; 44 static bool sw_ids_valid; 45 static u32 cpu_id; 46 static u32 unit_id; 47 48 #define SW0 IMX_GPIO_NR(2, 4) 49 #define SW1 IMX_GPIO_NR(2, 5) 50 #define SW2 IMX_GPIO_NR(2, 6) 51 #define SW3 IMX_GPIO_NR(2, 7) 52 #define HW0 IMX_GPIO_NR(6, 7) 53 #define HW1 IMX_GPIO_NR(6, 9) 54 #define HW2 IMX_GPIO_NR(6, 10) 55 #define HW3 IMX_GPIO_NR(6, 11) 56 #define HW4 IMX_GPIO_NR(4, 7) 57 #define HW5 IMX_GPIO_NR(4, 11) 58 #define HW6 IMX_GPIO_NR(4, 13) 59 #define HW7 IMX_GPIO_NR(4, 15) 60 61 int gpio_table_sw_ids[] = { 62 SW0, SW1, SW2, SW3 63 }; 64 65 const char *gpio_table_sw_ids_names[] = { 66 "sw0", "sw1", "sw2", "sw3" 67 }; 68 69 int gpio_table_hw_ids[] = { 70 HW0, HW1, HW2, HW3, HW4, HW5, HW6, HW7 71 }; 72 73 const char *gpio_table_hw_ids_names[] = { 74 "hw0", "hw1", "hw2", "hw3", "hw4", "hw5", "hw6", "hw7" 75 }; 76 77 static int get_board_id(int *ids, const char **c, int size, 78 bool *valid, u32 *id) 79 { 80 int i, ret, val; 81 82 *valid = false; 83 84 for (i = 0; i < size; i++) { 85 ret = gpio_request(ids[i], c[i]); 86 if (ret) { 87 printf("Can't request SWx gpios\n"); 88 return ret; 89 } 90 } 91 92 for (i = 0; i < size; i++) { 93 ret = gpio_direction_input(ids[i]); 94 if (ret) { 95 printf("Can't set SWx gpios direction\n"); 96 return ret; 97 } 98 } 99 100 for (i = 0; i < size; i++) { 101 val = gpio_get_value(ids[i]); 102 if (val < 0) { 103 printf("Can't get SW%d ID\n", i); 104 *id = 0; 105 return val; 106 } 107 *id |= val << i; 108 } 109 *valid = true; 110 111 return 0; 112 } 113 114 int dram_init(void) 115 { 116 gd->ram_size = imx_ddr_size(); 117 118 return 0; 119 } 120 121 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 122 /* I2C1: TFA9879 */ 123 struct i2c_pads_info i2c_pad_info0 = { 124 .scl = { 125 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, 126 .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC, 127 .gp = IMX_GPIO_NR(3, 21) 128 }, 129 .sda = { 130 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, 131 .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC, 132 .gp = IMX_GPIO_NR(3, 28) 133 } 134 }; 135 136 /* I2C2: TIVO TM4C123 */ 137 struct i2c_pads_info i2c_pad_info1 = { 138 .scl = { 139 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC, 140 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, 141 .gp = IMX_GPIO_NR(2, 30) 142 }, 143 .sda = { 144 .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC, 145 .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC, 146 .gp = IMX_GPIO_NR(3, 16) 147 } 148 }; 149 150 /* I2C3: PMIC PF0100, EEPROM AT24C256C */ 151 struct i2c_pads_info i2c_pad_info2 = { 152 .scl = { 153 .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC, 154 .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC, 155 .gp = IMX_GPIO_NR(3, 17) 156 }, 157 .sda = { 158 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, 159 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, 160 .gp = IMX_GPIO_NR(3, 18) 161 } 162 }; 163 164 iomux_v3_cfg_t const misc_pads[] = { 165 /* Prod ID GPIO pins */ 166 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), 167 MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), 168 MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), 169 MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), 170 171 /* HW revision GPIO pins */ 172 MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), 173 MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), 174 MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), 175 MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), 176 MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), 177 MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), 178 MX6_PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), 179 MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), 180 181 /* XTALOSC */ 182 MX6_PAD_GPIO_3__XTALOSC_REF_CLK_24M | MUX_PAD_CTRL(NO_PAD_CTRL), 183 }; 184 185 #ifdef CONFIG_FSL_ESDHC 186 struct fsl_esdhc_cfg usdhc_cfg[1] = { 187 { USDHC4_BASE_ADDR, 0, 8, }, 188 }; 189 190 int board_mmc_getcd(struct mmc *mmc) 191 { 192 return 1; 193 } 194 195 int board_mmc_init(bd_t *bis) 196 { 197 displ5_set_iomux_usdhc(); 198 199 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 200 201 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); 202 } 203 #endif /* CONFIG_FSL_ESDHC */ 204 205 static void displ5_setup_ecspi(void) 206 { 207 int ret; 208 209 displ5_set_iomux_ecspi(); 210 211 ret = gpio_request(IMX_GPIO_NR(5, 29), "spi2_cs0"); 212 if (!ret) 213 gpio_direction_output(IMX_GPIO_NR(5, 29), 1); 214 215 ret = gpio_request(IMX_GPIO_NR(7, 0), "spi2_#wp"); 216 if (!ret) 217 gpio_direction_output(IMX_GPIO_NR(7, 0), 1); 218 } 219 220 #ifdef CONFIG_FEC_MXC 221 iomux_v3_cfg_t const enet_pads[] = { 222 MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN | MUX_PAD_CTRL(ENET_PAD_CTRL), 223 MX6_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL), 224 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 225 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 226 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 227 228 /* for old evalboard with R159 present and R160 not populated */ 229 MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL), 230 231 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 232 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 233 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 234 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 235 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 236 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 237 238 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 239 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 240 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 241 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 242 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 243 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 244 /*INT#_GBE*/ 245 MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), 246 }; 247 248 static void setup_iomux_enet(void) 249 { 250 SETUP_IOMUX_PADS(enet_pads); 251 gpio_direction_input(IMX_GPIO_NR(1, 28)); /*INT#_GBE*/ 252 } 253 254 int board_eth_init(bd_t *bd) 255 { 256 struct phy_device *phydev; 257 struct mii_dev *bus; 258 int ret; 259 260 setup_iomux_enet(); 261 262 iomuxc_set_rgmii_io_voltage(DDR_SEL_1P5V_IO); 263 264 ret = enable_fec_anatop_clock(0, ENET_125MHZ); 265 if (ret) 266 return ret; 267 268 bus = fec_get_miibus(IMX_FEC_BASE, -1); 269 if (!bus) 270 return -ENODEV; 271 272 /* 273 * We use here the "rgmii-id" mode of operation and allow M88E1512 274 * PHY to use its internally callibrated RX/TX delays 275 */ 276 phydev = phy_find_by_mask(bus, 0xffffffff /* (0xf << 4) */, 277 PHY_INTERFACE_MODE_RGMII_ID); 278 if (!phydev) { 279 ret = -ENODEV; 280 goto err_phy; 281 } 282 283 /* display5 due to PCB routing can only work with 100 Mbps */ 284 phydev->advertising &= ~(ADVERTISED_1000baseX_Half | 285 ADVERTISED_1000baseX_Full | 286 SUPPORTED_1000baseT_Half | 287 SUPPORTED_1000baseT_Full); 288 289 ret = fec_probe(bd, -1, IMX_FEC_BASE, bus, phydev); 290 if (ret) 291 goto err_sw; 292 293 return 0; 294 295 err_sw: 296 free(phydev); 297 err_phy: 298 mdio_unregister(bus); 299 free(bus); 300 return ret; 301 } 302 #endif /* CONFIG_FEC_MXC */ 303 304 /* 305 * Do not overwrite the console 306 * Always use serial for U-Boot console 307 */ 308 int overwrite_console(void) 309 { 310 return 1; 311 } 312 313 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) 314 int ft_board_setup(void *blob, bd_t *bd) 315 { 316 fdt_fixup_ethernet(blob); 317 return 0; 318 } 319 #endif 320 321 int board_init(void) 322 { 323 debug("board init\n"); 324 /* address of boot parameters */ 325 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 326 327 /* Setup iomux for non console UARTS */ 328 displ5_set_iomux_uart(); 329 330 displ5_setup_ecspi(); 331 332 SETUP_IOMUX_PADS(misc_pads); 333 334 get_board_id(gpio_table_sw_ids, &gpio_table_sw_ids_names[0], 335 ARRAY_SIZE(gpio_table_sw_ids), &sw_ids_valid, &unit_id); 336 debug("SWx unit_id 0x%x\n", unit_id); 337 338 get_board_id(gpio_table_hw_ids, &gpio_table_hw_ids_names[0], 339 ARRAY_SIZE(gpio_table_hw_ids), &hw_ids_valid, &cpu_id); 340 debug("HWx cpu_id 0x%x\n", cpu_id); 341 342 if (hw_ids_valid && sw_ids_valid) 343 printf("ID: unit type 0x%x rev 0x%x\n", unit_id, cpu_id); 344 345 udelay(25); 346 347 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); 348 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 349 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); 350 351 return 0; 352 } 353 354 #ifdef CONFIG_CMD_BMODE 355 static const struct boot_mode board_boot_modes[] = { 356 /* eMMC, USDHC-4, 8-bit bus width */ 357 /* SPI-NOR, ECSPI-2 SS0, 3-bytes addressing */ 358 {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)}, 359 {"spinor", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x09)}, 360 {NULL, 0}, 361 }; 362 363 static void setup_boot_modes(void) 364 { 365 add_board_boot_modes(board_boot_modes); 366 } 367 #else 368 static inline void setup_boot_modes(void) {} 369 #endif 370 371 int misc_init_r(void) 372 { 373 setup_boot_modes(); 374 return 0; 375 } 376 377 static struct mxc_serial_platdata mxc_serial_plat = { 378 .reg = (struct mxc_uart *)UART5_BASE, 379 }; 380 381 U_BOOT_DEVICE(mxc_serial) = { 382 .name = "serial_mxc", 383 .platdata = &mxc_serial_plat, 384 }; 385