1*a3eec24aSLukasz Majewski /* 2*a3eec24aSLukasz Majewski * Copyright (C) 2017 DENX Software Engineering 3*a3eec24aSLukasz Majewski * Lukasz Majewski, DENX Software Engineering, lukma@denx.de 4*a3eec24aSLukasz Majewski * 5*a3eec24aSLukasz Majewski * SPDX-License-Identifier: GPL-2.0+ 6*a3eec24aSLukasz Majewski */ 7*a3eec24aSLukasz Majewski 8*a3eec24aSLukasz Majewski #ifndef __DISPL5_COMMON_H_ 9*a3eec24aSLukasz Majewski #define __DISPL5_COMMON_H_ 10*a3eec24aSLukasz Majewski 11*a3eec24aSLukasz Majewski #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 12*a3eec24aSLukasz Majewski PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 13*a3eec24aSLukasz Majewski PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 14*a3eec24aSLukasz Majewski 15*a3eec24aSLukasz Majewski #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 16*a3eec24aSLukasz Majewski PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ 17*a3eec24aSLukasz Majewski PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 18*a3eec24aSLukasz Majewski 19*a3eec24aSLukasz Majewski #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 20*a3eec24aSLukasz Majewski PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_MED | \ 21*a3eec24aSLukasz Majewski PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 22*a3eec24aSLukasz Majewski 23*a3eec24aSLukasz Majewski #define SPI_PAD_CTRL (PAD_CTL_HYS | \ 24*a3eec24aSLukasz Majewski PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ 25*a3eec24aSLukasz Majewski PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 26*a3eec24aSLukasz Majewski 27*a3eec24aSLukasz Majewski #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 28*a3eec24aSLukasz Majewski PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 29*a3eec24aSLukasz Majewski PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 30*a3eec24aSLukasz Majewski PAD_CTL_ODE | PAD_CTL_SRE_FAST) 31*a3eec24aSLukasz Majewski 32*a3eec24aSLukasz Majewski #define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \ 33*a3eec24aSLukasz Majewski PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 34*a3eec24aSLukasz Majewski 35*a3eec24aSLukasz Majewski void displ5_set_iomux_uart_spl(void); 36*a3eec24aSLukasz Majewski void displ5_set_iomux_uart(void); 37*a3eec24aSLukasz Majewski void displ5_set_iomux_ecspi_spl(void); 38*a3eec24aSLukasz Majewski void displ5_set_iomux_ecspi(void); 39*a3eec24aSLukasz Majewski void displ5_set_iomux_usdhc_spl(void); 40*a3eec24aSLukasz Majewski void displ5_set_iomux_usdhc(void); 41*a3eec24aSLukasz Majewski 42*a3eec24aSLukasz Majewski #endif /* __DISPL5_COMMON_H_ */ 43