1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 */ 4 5 #include <common.h> 6 #include <asm/io.h> 7 #include <asm/arch/sama5_sfr.h> 8 #include <asm/arch/sama5d3_smc.h> 9 #include <asm/arch/at91_common.h> 10 #include <asm/arch/at91_pmc.h> 11 #include <asm/arch/at91_rstc.h> 12 #include <asm/arch/gpio.h> 13 #include <asm/arch/clk.h> 14 #include <micrel.h> 15 #include <net.h> 16 #include <netdev.h> 17 #include <spl.h> 18 #include <asm/arch/atmel_mpddrc.h> 19 #include <asm/arch/at91_wdt.h> 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 /* ------------------------------------------------------------------------- */ 24 /* 25 * Miscelaneous platform dependent initialisations 26 */ 27 28 void wb50n_nand_hw_init(void) 29 { 30 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 31 32 at91_periph_clk_enable(ATMEL_ID_SMC); 33 34 /* Configure SMC CS3 for NAND/SmartMedia */ 35 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) | 36 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1), 37 &smc->cs[3].setup); 38 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | 39 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5), 40 &smc->cs[3].pulse); 41 writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8), 42 &smc->cs[3].cycle); 43 writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) | 44 AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) | 45 AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3) | 46 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); 47 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 48 AT91_SMC_MODE_EXNW_DISABLE | 49 AT91_SMC_MODE_DBW_8 | 50 AT91_SMC_MODE_TDF_CYCLE(3), &smc->cs[3].mode); 51 52 /* Disable Flash Write Protect Line */ 53 at91_set_pio_output(AT91_PIO_PORTE, 14, 1); 54 } 55 56 int board_early_init_f(void) 57 { 58 at91_periph_clk_enable(ATMEL_ID_PIOA); 59 at91_periph_clk_enable(ATMEL_ID_PIOB); 60 at91_periph_clk_enable(ATMEL_ID_PIOC); 61 at91_periph_clk_enable(ATMEL_ID_PIOD); 62 at91_periph_clk_enable(ATMEL_ID_PIOE); 63 64 at91_seriald_hw_init(); 65 66 return 0; 67 } 68 69 int board_init(void) 70 { 71 /* adress of boot parameters */ 72 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 73 74 wb50n_nand_hw_init(); 75 76 at91_macb_hw_init(); 77 78 return 0; 79 } 80 81 int dram_init(void) 82 { 83 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 84 CONFIG_SYS_SDRAM_SIZE); 85 return 0; 86 } 87 88 int board_phy_config(struct phy_device *phydev) 89 { 90 /* rx data delay */ 91 ksz9021_phy_extended_write(phydev, 92 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x2222); 93 /* tx data delay */ 94 ksz9021_phy_extended_write(phydev, 95 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x2222); 96 /* rx/tx clock delay */ 97 ksz9021_phy_extended_write(phydev, 98 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf2f4); 99 100 return 0; 101 } 102 103 int board_eth_init(bd_t *bis) 104 { 105 int rc = 0; 106 107 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); 108 109 return rc; 110 } 111 112 #ifdef CONFIG_BOARD_LATE_INIT 113 #include <linux/ctype.h> 114 int board_late_init(void) 115 { 116 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 117 const char *LAIRD_NAME = "lrd_name"; 118 char name[32], *p; 119 120 strcpy(name, get_cpu_name()); 121 for (p = name; *p != '\0'; *p = tolower(*p), p++) 122 ; 123 strcat(name, "-wb50n"); 124 env_set(LAIRD_NAME, name); 125 126 #endif 127 128 return 0; 129 } 130 #endif 131 132 /* SPL */ 133 #ifdef CONFIG_SPL_BUILD 134 void spl_board_init(void) 135 { 136 wb50n_nand_hw_init(); 137 } 138 139 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) 140 { 141 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_LPDDR_SDRAM); 142 143 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_9 | 144 ATMEL_MPDDRC_CR_NR_ROW_13 | 145 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | 146 ATMEL_MPDDRC_CR_NDQS_DISABLED | 147 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | 148 ATMEL_MPDDRC_CR_UNAL_SUPPORTED); 149 150 ddr2->rtr = 0x411; 151 152 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | 153 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | 154 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | 155 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | 156 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | 157 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | 158 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | 159 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); 160 161 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | 162 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | 163 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | 164 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); 165 166 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | 167 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | 168 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | 169 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | 170 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); 171 } 172 173 void mem_init(void) 174 { 175 struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR; 176 struct atmel_mpddrc_config ddr2; 177 178 ddr2_conf(&ddr2); 179 180 writel(ATMEL_SFR_DDRCFG_FDQIEN | ATMEL_SFR_DDRCFG_FDQSIEN, 181 &sfr->ddrcfg); 182 183 /* enable MPDDR clock */ 184 at91_periph_clk_enable(ATMEL_ID_MPDDRC); 185 at91_system_clk_enable(AT91_PMC_DDR); 186 187 /* DDRAM2 Controller initialize */ 188 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); 189 } 190 191 void at91_pmc_init(void) 192 { 193 u32 tmp; 194 195 tmp = AT91_PMC_PLLAR_29 | 196 AT91_PMC_PLLXR_PLLCOUNT(0x3f) | 197 AT91_PMC_PLLXR_MUL(43) | AT91_PMC_PLLXR_DIV(1); 198 at91_plla_init(tmp); 199 200 at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3)); 201 202 tmp = AT91_PMC_MCKR_MDIV_4 | AT91_PMC_MCKR_CSS_PLLA; 203 at91_mck_init(tmp); 204 } 205 #endif 206