1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 */ 4 5 #include <common.h> 6 #include <asm/io.h> 7 #include <asm/arch/at91sam9x5_matrix.h> 8 #include <asm/arch/at91sam9_smc.h> 9 #include <asm/arch/at91_common.h> 10 #include <asm/arch/at91_rstc.h> 11 #include <asm/arch/clk.h> 12 #include <asm/arch/gpio.h> 13 #include <net.h> 14 #include <netdev.h> 15 16 DECLARE_GLOBAL_DATA_PTR; 17 18 /* ------------------------------------------------------------------------- */ 19 /* 20 * Miscelaneous platform dependent initialisations 21 */ 22 static void wb45n_nand_hw_init(void) 23 { 24 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 25 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 26 unsigned long csa; 27 28 csa = readl(&matrix->ebicsa); 29 /* Enable CS3 */ 30 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; 31 /* NAND flash on D0 */ 32 csa &= ~AT91_MATRIX_NFD0_ON_D16; 33 writel(csa, &matrix->ebicsa); 34 35 /* Configure SMC CS3 for NAND/SmartMedia */ 36 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | 37 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), 38 &smc->cs[3].setup); 39 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | 40 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6), 41 &smc->cs[3].pulse); 42 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6), 43 &smc->cs[3].cycle); 44 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 45 AT91_SMC_MODE_EXNW_DISABLE | 46 AT91_SMC_MODE_DBW_8 | 47 AT91_SMC_MODE_TDF_CYCLE(1), &smc->cs[3].mode); 48 49 at91_periph_clk_enable(ATMEL_ID_PIOCD); 50 51 /* Configure RDY/BSY */ 52 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); 53 /* Enable NandFlash */ 54 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 55 /* Disable Flash Write Protect Line */ 56 at91_set_gpio_output(AT91_PIN_PD10, 1); 57 58 at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ 59 at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ 60 at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */ 61 at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */ 62 } 63 64 static void wb45n_gpio_hw_init(void) 65 { 66 67 /* Configure wifi gpio CHIP_PWD_L */ 68 at91_set_gpio_output(AT91_PIN_PA28, 0); 69 70 /* Setup USB pins */ 71 at91_set_gpio_input(AT91_PIN_PB11, 0); 72 at91_set_gpio_output(AT91_PIN_PB12, 0); 73 74 /* IRQ pin, pullup, deglitch */ 75 at91_set_gpio_input(AT91_PIN_PB18, 1); 76 at91_set_gpio_deglitch(AT91_PIN_PB18, 1); 77 } 78 79 int board_eth_init(bd_t *bis) 80 { 81 int rc = 0; 82 83 if (has_emac0()) 84 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00); 85 86 return rc; 87 } 88 89 int board_early_init_f(void) 90 { 91 at91_seriald_hw_init(); 92 return 0; 93 } 94 95 int board_init(void) 96 { 97 /* address of boot parameters */ 98 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 99 100 wb45n_gpio_hw_init(); 101 102 wb45n_nand_hw_init(); 103 104 at91_macb_hw_init(); 105 106 return 0; 107 } 108 109 int dram_init(void) 110 { 111 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 112 CONFIG_SYS_SDRAM_SIZE); 113 return 0; 114 } 115 116 #if defined(CONFIG_SPL_BUILD) 117 #include <spl.h> 118 #include <nand.h> 119 120 void at91_spl_board_init(void) 121 { 122 /* Setup GPIO first */ 123 wb45n_gpio_hw_init(); 124 125 /* Bring up NAND */ 126 wb45n_nand_hw_init(); 127 } 128 129 void matrix_init(void) 130 { 131 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 132 unsigned long csa; 133 134 csa = readl(&matrix->ebicsa); 135 /* Pull ups on D0 - D16 */ 136 csa &= ~AT91_MATRIX_EBI_DBPU_OFF; 137 csa |= AT91_MATRIX_EBI_DBPD_OFF; 138 /* Normal drive strength */ 139 csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL; 140 /* Multi-port off */ 141 csa &= ~AT91_MATRIX_MP_ON; 142 writel(csa, &matrix->ebicsa); 143 } 144 145 #include <asm/arch/atmel_mpddrc.h> 146 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) 147 { 148 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_LPDDR_SDRAM); 149 150 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 151 ATMEL_MPDDRC_CR_NR_ROW_13 | 152 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | 153 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | 154 ATMEL_MPDDRC_CR_DQMS_SHARED); 155 156 ddr2->rtr = 0x411; 157 158 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | 159 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | 160 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | 161 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | 162 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | 163 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | 164 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | 165 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); 166 167 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | 168 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | 169 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | 170 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); 171 172 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | 173 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | 174 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | 175 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | 176 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); 177 } 178 179 void mem_init(void) 180 { 181 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 182 struct atmel_mpddrc_config ddr2; 183 unsigned long csa; 184 185 ddr2_conf(&ddr2); 186 187 /* enable DDR2 clock */ 188 at91_system_clk_enable(AT91_PMC_DDR); 189 190 /* Chip select 1 is for DDR2/SDRAM */ 191 csa = readl(&matrix->ebicsa); 192 csa |= AT91_MATRIX_EBI_CS1A_SDRAMC; 193 writel(csa, &matrix->ebicsa); 194 195 /* DDRAM2 Controller initialize */ 196 ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2); 197 } 198 #endif 199