1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Novena video output support 4 * 5 * IT6251 code based on code Copyright (C) 2014 Sean Cross 6 * from https://github.com/xobs/novena-linux.git commit 7 * 3d85836ee1377d445531928361809612aa0a18db 8 * 9 * Copyright (C) 2014 Marek Vasut <marex@denx.de> 10 */ 11 12 #include <common.h> 13 #include <linux/errno.h> 14 #include <asm/gpio.h> 15 #include <asm/io.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/crm_regs.h> 18 #include <asm/arch/imx-regs.h> 19 #include <asm/arch/iomux.h> 20 #include <asm/arch/mxc_hdmi.h> 21 #include <asm/arch/sys_proto.h> 22 #include <asm/mach-imx/iomux-v3.h> 23 #include <asm/mach-imx/mxc_i2c.h> 24 #include <asm/mach-imx/video.h> 25 #include <i2c.h> 26 #include <input.h> 27 #include <ipu_pixfmt.h> 28 #include <linux/fb.h> 29 #include <linux/input.h> 30 #include <malloc.h> 31 #include <stdio_dev.h> 32 33 #include "novena.h" 34 35 #define IT6251_VENDOR_ID_LOW 0x00 36 #define IT6251_VENDOR_ID_HIGH 0x01 37 #define IT6251_DEVICE_ID_LOW 0x02 38 #define IT6251_DEVICE_ID_HIGH 0x03 39 #define IT6251_SYSTEM_STATUS 0x0d 40 #define IT6251_SYSTEM_STATUS_RINTSTATUS (1 << 0) 41 #define IT6251_SYSTEM_STATUS_RHPDSTATUS (1 << 1) 42 #define IT6251_SYSTEM_STATUS_RVIDEOSTABLE (1 << 2) 43 #define IT6251_SYSTEM_STATUS_RPLL_IOLOCK (1 << 3) 44 #define IT6251_SYSTEM_STATUS_RPLL_XPLOCK (1 << 4) 45 #define IT6251_SYSTEM_STATUS_RPLL_SPLOCK (1 << 5) 46 #define IT6251_SYSTEM_STATUS_RAUXFREQ_LOCK (1 << 6) 47 #define IT6251_REF_STATE 0x0e 48 #define IT6251_REF_STATE_MAIN_LINK_DISABLED (1 << 0) 49 #define IT6251_REF_STATE_AUX_CHANNEL_READ (1 << 1) 50 #define IT6251_REF_STATE_CR_PATTERN (1 << 2) 51 #define IT6251_REF_STATE_EQ_PATTERN (1 << 3) 52 #define IT6251_REF_STATE_NORMAL_OPERATION (1 << 4) 53 #define IT6251_REF_STATE_MUTED (1 << 5) 54 55 #define IT6251_REG_PCLK_CNT_LOW 0x57 56 #define IT6251_REG_PCLK_CNT_HIGH 0x58 57 58 #define IT6521_RETRY_MAX 20 59 60 static int it6251_is_stable(void) 61 { 62 const unsigned int caddr = NOVENA_IT6251_CHIPADDR; 63 const unsigned int laddr = NOVENA_IT6251_LVDSADDR; 64 int status; 65 int clkcnt; 66 int rpclkcnt; 67 int refstate; 68 69 rpclkcnt = (i2c_reg_read(caddr, 0x13) & 0xff) | 70 ((i2c_reg_read(caddr, 0x14) << 8) & 0x0f00); 71 debug("RPCLKCnt: %d\n", rpclkcnt); 72 73 status = i2c_reg_read(caddr, IT6251_SYSTEM_STATUS); 74 debug("System status: 0x%02x\n", status); 75 76 clkcnt = (i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_LOW) & 0xff) | 77 ((i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_HIGH) << 8) & 78 0x0f00); 79 debug("Clock: 0x%02x\n", clkcnt); 80 81 refstate = i2c_reg_read(laddr, IT6251_REF_STATE); 82 debug("Ref Link State: 0x%02x\n", refstate); 83 84 if ((refstate & 0x1f) != 0) 85 return 0; 86 87 /* If video is muted, that's a failure */ 88 if (refstate & IT6251_REF_STATE_MUTED) 89 return 0; 90 91 if (!(status & IT6251_SYSTEM_STATUS_RVIDEOSTABLE)) 92 return 0; 93 94 return 1; 95 } 96 97 static int it6251_ready(void) 98 { 99 const unsigned int caddr = NOVENA_IT6251_CHIPADDR; 100 101 /* Test if the IT6251 came out of reset by reading ID regs. */ 102 if (i2c_reg_read(caddr, IT6251_VENDOR_ID_LOW) != 0x15) 103 return 0; 104 if (i2c_reg_read(caddr, IT6251_VENDOR_ID_HIGH) != 0xca) 105 return 0; 106 if (i2c_reg_read(caddr, IT6251_DEVICE_ID_LOW) != 0x51) 107 return 0; 108 if (i2c_reg_read(caddr, IT6251_DEVICE_ID_HIGH) != 0x62) 109 return 0; 110 111 return 1; 112 } 113 114 static void it6251_program_regs(void) 115 { 116 const unsigned int caddr = NOVENA_IT6251_CHIPADDR; 117 const unsigned int laddr = NOVENA_IT6251_LVDSADDR; 118 119 i2c_reg_write(caddr, 0x05, 0x00); 120 mdelay(1); 121 122 /* set LVDSRX address, and enable */ 123 i2c_reg_write(caddr, 0xfd, 0xbc); 124 i2c_reg_write(caddr, 0xfe, 0x01); 125 126 /* 127 * LVDSRX 128 */ 129 /* This write always fails, because the chip goes into reset */ 130 /* reset LVDSRX */ 131 i2c_reg_write(laddr, 0x05, 0xff); 132 i2c_reg_write(laddr, 0x05, 0x00); 133 134 /* reset LVDSRX PLL */ 135 i2c_reg_write(laddr, 0x3b, 0x42); 136 i2c_reg_write(laddr, 0x3b, 0x43); 137 138 /* something with SSC PLL */ 139 i2c_reg_write(laddr, 0x3c, 0x08); 140 /* don't swap links, but writing reserved registers */ 141 i2c_reg_write(laddr, 0x0b, 0x88); 142 143 /* JEIDA, 8-bit depth 0x11, orig 0x42 */ 144 i2c_reg_write(laddr, 0x2c, 0x01); 145 /* "reserved" */ 146 i2c_reg_write(laddr, 0x32, 0x04); 147 /* "reserved" */ 148 i2c_reg_write(laddr, 0x35, 0xe0); 149 /* "reserved" + clock delay */ 150 i2c_reg_write(laddr, 0x2b, 0x24); 151 152 /* reset LVDSRX pix clock */ 153 i2c_reg_write(laddr, 0x05, 0x02); 154 i2c_reg_write(laddr, 0x05, 0x00); 155 156 /* 157 * DPTX 158 */ 159 /* set for two lane mode, normal op, no swapping, no downspread */ 160 i2c_reg_write(caddr, 0x16, 0x02); 161 162 /* some AUX channel EDID magic */ 163 i2c_reg_write(caddr, 0x23, 0x40); 164 165 /* power down lanes 3-0 */ 166 i2c_reg_write(caddr, 0x5c, 0xf3); 167 168 /* enable DP scrambling, change EQ CR phase */ 169 i2c_reg_write(caddr, 0x5f, 0x06); 170 171 /* color mode RGB, pclk/2 */ 172 i2c_reg_write(caddr, 0x60, 0x02); 173 /* dual pixel input mode, no EO swap, no RGB swap */ 174 i2c_reg_write(caddr, 0x61, 0x04); 175 /* M444B24 video format */ 176 i2c_reg_write(caddr, 0x62, 0x01); 177 178 /* vesa range / not interlace / vsync high / hsync high */ 179 i2c_reg_write(caddr, 0xa0, 0x0F); 180 181 /* hpd event timer set to 1.6-ish ms */ 182 i2c_reg_write(caddr, 0xc9, 0xf5); 183 184 /* more reserved magic */ 185 i2c_reg_write(caddr, 0xca, 0x4d); 186 i2c_reg_write(caddr, 0xcb, 0x37); 187 188 /* enhanced framing mode, auto video fifo reset, video mute disable */ 189 i2c_reg_write(caddr, 0xd3, 0x03); 190 191 /* "vidstmp" and some reserved stuff */ 192 i2c_reg_write(caddr, 0xd4, 0x45); 193 194 /* queue number -- reserved */ 195 i2c_reg_write(caddr, 0xe7, 0xa0); 196 /* info frame packets and reserved */ 197 i2c_reg_write(caddr, 0xe8, 0x33); 198 /* more AVI stuff */ 199 i2c_reg_write(caddr, 0xec, 0x00); 200 201 /* select PC master reg for aux channel? */ 202 i2c_reg_write(caddr, 0x23, 0x42); 203 204 /* send PC request commands */ 205 i2c_reg_write(caddr, 0x24, 0x00); 206 i2c_reg_write(caddr, 0x25, 0x00); 207 i2c_reg_write(caddr, 0x26, 0x00); 208 209 /* native aux read */ 210 i2c_reg_write(caddr, 0x2b, 0x00); 211 /* back to internal */ 212 i2c_reg_write(caddr, 0x23, 0x40); 213 214 /* voltage swing level 3 */ 215 i2c_reg_write(caddr, 0x19, 0xff); 216 /* pre-emphasis level 3 */ 217 i2c_reg_write(caddr, 0x1a, 0xff); 218 219 /* start link training */ 220 i2c_reg_write(caddr, 0x17, 0x01); 221 } 222 223 static int it6251_init(void) 224 { 225 const unsigned int caddr = NOVENA_IT6251_CHIPADDR; 226 int reg; 227 int tries, retries = 0; 228 229 for (retries = 0; retries < IT6521_RETRY_MAX; retries++) { 230 /* Program the chip. */ 231 it6251_program_regs(); 232 233 /* Wait for video stable. */ 234 for (tries = 0; tries < 100; tries++) { 235 reg = i2c_reg_read(caddr, 0x17); 236 /* Test Link CFG, STS, LCS read done. */ 237 if ((reg & 0xe0) != 0xe0) { 238 /* Not yet, wait a bit more. */ 239 mdelay(2); 240 continue; 241 } 242 243 /* Test if the video input is stable. */ 244 if (it6251_is_stable()) 245 return 0; 246 } 247 /* 248 * If we couldn't stabilize, requeue and try again, 249 * because it means that the LVDS channel isn't 250 * stable yet. 251 */ 252 printf("Display didn't stabilize.\n"); 253 printf("This may be because the LVDS port is still in powersave mode.\n"); 254 mdelay(50); 255 } 256 257 return -EINVAL; 258 } 259 260 static void enable_hdmi(struct display_info_t const *dev) 261 { 262 imx_enable_hdmi_phy(); 263 } 264 265 static int lvds_enabled; 266 267 static void enable_lvds(struct display_info_t const *dev) 268 { 269 if (lvds_enabled) 270 return; 271 272 /* ITE IT6251 power enable. */ 273 gpio_direction_output(NOVENA_ITE6251_PWR_GPIO, 0); 274 mdelay(10); 275 gpio_direction_output(NOVENA_ITE6251_PWR_GPIO, 1); 276 mdelay(20); 277 lvds_enabled = 1; 278 } 279 280 static int detect_lvds(struct display_info_t const *dev) 281 { 282 int ret, loops = 250; 283 284 enable_lvds(dev); 285 286 ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS); 287 if (ret) { 288 puts("Cannot select IT6251 I2C bus.\n"); 289 return 0; 290 } 291 292 /* Wait up-to ~250 mS for the LVDS to come up. */ 293 while (--loops) { 294 ret = it6251_ready(); 295 if (ret) 296 return ret; 297 298 mdelay(1); 299 } 300 301 return 0; 302 } 303 304 struct display_info_t const displays[] = { 305 { 306 /* HDMI Output */ 307 .bus = -1, 308 .addr = 0, 309 .pixfmt = IPU_PIX_FMT_RGB24, 310 .detect = detect_hdmi, 311 .enable = enable_hdmi, 312 .mode = { 313 .name = "HDMI", 314 .refresh = 60, 315 .xres = 1024, 316 .yres = 768, 317 .pixclock = 15384, 318 .left_margin = 220, 319 .right_margin = 40, 320 .upper_margin = 21, 321 .lower_margin = 7, 322 .hsync_len = 60, 323 .vsync_len = 10, 324 .sync = FB_SYNC_EXT, 325 .vmode = FB_VMODE_NONINTERLACED 326 }, 327 }, { 328 /* LVDS Output: N133HSE-EA1 Rev. C1 */ 329 .bus = -1, 330 .pixfmt = IPU_PIX_FMT_RGB24, 331 .detect = detect_lvds, 332 .enable = enable_lvds, 333 .mode = { 334 .name = "Chimei-FHD", 335 .refresh = 60, 336 .xres = 1920, 337 .yres = 1080, 338 .pixclock = 15384, 339 .left_margin = 148, 340 .right_margin = 88, 341 .upper_margin = 36, 342 .lower_margin = 4, 343 .hsync_len = 44, 344 .vsync_len = 5, 345 .sync = FB_SYNC_HOR_HIGH_ACT | 346 FB_SYNC_VERT_HIGH_ACT | 347 FB_SYNC_EXT, 348 .vmode = FB_VMODE_NONINTERLACED, 349 }, 350 }, 351 }; 352 353 size_t display_count = ARRAY_SIZE(displays); 354 355 static void enable_vpll(void) 356 { 357 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 358 int timeout = 100000; 359 360 setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN); 361 362 clrsetbits_le32(&ccm->analog_pll_video, 363 BM_ANADIG_PLL_VIDEO_DIV_SELECT | 364 BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT, 365 BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) | 366 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1)); 367 368 writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num); 369 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom); 370 371 clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN); 372 373 while (timeout--) 374 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) 375 break; 376 if (timeout < 0) 377 printf("Warning: video pll lock timeout!\n"); 378 379 clrsetbits_le32(&ccm->analog_pll_video, 380 BM_ANADIG_PLL_VIDEO_BYPASS, 381 BM_ANADIG_PLL_VIDEO_ENABLE); 382 } 383 384 void setup_display_clock(void) 385 { 386 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 387 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 388 389 enable_ipu_clock(); 390 enable_vpll(); 391 imx_setup_hdmi(); 392 393 /* Turn on IPU LDB DI0 clocks */ 394 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); 395 396 /* Switch LDB DI0 to PLL5 (Video PLL) */ 397 clrsetbits_le32(&mxc_ccm->cs2cdr, 398 MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK, 399 (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)); 400 401 /* LDB clock div by 3.5 */ 402 clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); 403 404 /* DI0 clock derived from ldb_di0_clk */ 405 clrsetbits_le32(&mxc_ccm->chsccdr, 406 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK, 407 (CHSCCDR_CLK_SEL_LDB_DI0 << 408 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET) 409 ); 410 411 /* Enable both LVDS channels, both connected to DI0. */ 412 writel(IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH | 413 IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA | 414 IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT | 415 IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA | 416 IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT | 417 IOMUXC_GPR2_SPLIT_MODE_EN_MASK | 418 IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 | 419 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0, 420 &iomux->gpr[2]); 421 422 clrsetbits_le32(&iomux->gpr[3], 423 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK | 424 IOMUXC_GPR3_LVDS1_MUX_CTL_MASK, 425 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << 426 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) | 427 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << 428 IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET) 429 ); 430 } 431 432 void setup_display_lvds(void) 433 { 434 int ret; 435 436 ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS); 437 if (ret) { 438 puts("Cannot select LVDS-to-eDP I2C bus.\n"); 439 return; 440 } 441 442 /* The IT6251 should be ready now, if it's not, it's not connected. */ 443 ret = it6251_ready(); 444 if (!ret) 445 return; 446 447 /* Init the LVDS-to-eDP chip and if it succeeded, enable backlight. */ 448 ret = it6251_init(); 449 if (!ret) { 450 /* Backlight power enable. */ 451 gpio_direction_output(NOVENA_BACKLIGHT_PWR_GPIO, 1); 452 /* PWM backlight pin, always on for full brightness. */ 453 gpio_direction_output(NOVENA_BACKLIGHT_PWM_GPIO, 1); 454 } 455 } 456