1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Novena SPL 4 * 5 * Copyright (C) 2014 Marek Vasut <marex@denx.de> 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/arch/clock.h> 11 #include <asm/arch/iomux.h> 12 #include <asm/arch/mx6-ddr.h> 13 #include <asm/arch/mx6-pins.h> 14 #include <asm/arch/sys_proto.h> 15 #include <asm/gpio.h> 16 #include <asm/mach-imx/boot_mode.h> 17 #include <asm/mach-imx/iomux-v3.h> 18 #include <asm/mach-imx/mxc_i2c.h> 19 #include <asm/arch/crm_regs.h> 20 #include <i2c.h> 21 #include <mmc.h> 22 #include <fsl_esdhc.h> 23 #include <spl.h> 24 25 #include <asm/arch/mx6-ddr.h> 26 27 #include "novena.h" 28 29 #define UART_PAD_CTRL \ 30 (PAD_CTL_PKE | PAD_CTL_PUE | \ 31 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 32 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 33 34 #define USDHC_PAD_CTRL \ 35 (PAD_CTL_PKE | PAD_CTL_PUE | \ 36 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ 37 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 38 39 #define ENET_PAD_CTRL \ 40 (PAD_CTL_PKE | PAD_CTL_PUE | \ 41 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 42 PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 43 44 #define ENET_PHY_CFG_PAD_CTRL \ 45 (PAD_CTL_PKE | PAD_CTL_PUE | \ 46 PAD_CTL_PUS_22K_UP | PAD_CTL_HYS) 47 48 #define RGMII_PAD_CTRL \ 49 (PAD_CTL_PKE | PAD_CTL_PUE | \ 50 PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 51 52 #define SPI_PAD_CTRL \ 53 (PAD_CTL_HYS | \ 54 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ 55 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 56 57 #define I2C_PAD_CTRL \ 58 (PAD_CTL_PKE | PAD_CTL_PUE | \ 59 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ 60 PAD_CTL_DSE_240ohm | PAD_CTL_HYS | \ 61 PAD_CTL_ODE) 62 63 #define BUTTON_PAD_CTRL \ 64 (PAD_CTL_PKE | PAD_CTL_PUE | \ 65 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 66 PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 67 68 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 69 70 /* 71 * Audio 72 */ 73 static iomux_v3_cfg_t audio_pads[] = { 74 /* AUD_PWRON */ 75 MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), 76 }; 77 78 static void novena_spl_setup_iomux_audio(void) 79 { 80 imx_iomux_v3_setup_multiple_pads(audio_pads, ARRAY_SIZE(audio_pads)); 81 gpio_direction_output(NOVENA_AUDIO_PWRON, 1); 82 } 83 84 /* 85 * ENET 86 */ 87 static iomux_v3_cfg_t enet_pads1[] = { 88 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 89 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 90 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(RGMII_PAD_CTRL), 91 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(RGMII_PAD_CTRL), 92 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(RGMII_PAD_CTRL), 93 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(RGMII_PAD_CTRL), 94 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(RGMII_PAD_CTRL), 95 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(RGMII_PAD_CTRL), 96 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 97 98 /* pin 35, PHY_AD2 */ 99 MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL), 100 /* pin 32, MODE0 */ 101 MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL), 102 /* pin 31, MODE1 */ 103 MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL), 104 /* pin 28, MODE2 */ 105 MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL), 106 /* pin 27, MODE3 */ 107 MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL), 108 /* pin 33, CLK125_EN */ 109 MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL), 110 111 /* pin 42 PHY nRST */ 112 MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), 113 }; 114 115 static iomux_v3_cfg_t enet_pads2[] = { 116 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(RGMII_PAD_CTRL), 117 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(RGMII_PAD_CTRL), 118 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(RGMII_PAD_CTRL), 119 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(RGMII_PAD_CTRL), 120 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(RGMII_PAD_CTRL), 121 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(RGMII_PAD_CTRL), 122 }; 123 124 static void novena_spl_setup_iomux_enet(void) 125 { 126 imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); 127 128 /* Assert Ethernet PHY nRST */ 129 gpio_direction_output(IMX_GPIO_NR(3, 23), 0); 130 131 /* 132 * Use imx6 internal pull-ups to drive PHY mode pins during PHY reset 133 * de-assertion. The intention is to use weak signal drivers (pull-ups) 134 * to prevent the conflict between PHY pins becoming outputs after 135 * reset and imx6 still driving the pins. The issue is described in PHY 136 * datasheet, p.14 137 */ 138 gpio_direction_input(IMX_GPIO_NR(6, 30)); /* PHY_AD2 = 1 */ 139 gpio_direction_input(IMX_GPIO_NR(6, 25)); /* MODE0 = 1 */ 140 gpio_direction_input(IMX_GPIO_NR(6, 27)); /* MODE1 = 1 */ 141 gpio_direction_input(IMX_GPIO_NR(6, 28)); /* MODE2 = 1 */ 142 gpio_direction_input(IMX_GPIO_NR(6, 29)); /* MODE3 = 1 */ 143 gpio_direction_input(IMX_GPIO_NR(6, 24)); /* CLK125_EN = 1 */ 144 145 /* Following reset timing (p.53, fig.8 from the PHY datasheet) */ 146 mdelay(10); 147 148 /* De-assert Ethernet PHY nRST */ 149 gpio_set_value(IMX_GPIO_NR(3, 23), 1); 150 151 /* PHY is now configured, connect FEC to the pads */ 152 imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); 153 154 /* 155 * PHY datasheet recommends on p.53 to wait at least 100us after reset 156 * before using MII, so we enforce the delay here 157 */ 158 udelay(100); 159 } 160 161 /* 162 * FPGA 163 */ 164 static iomux_v3_cfg_t fpga_pads[] = { 165 /* FPGA_RESET_N */ 166 MX6_PAD_DISP0_DAT13__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), 167 }; 168 169 static void novena_spl_setup_iomux_fpga(void) 170 { 171 imx_iomux_v3_setup_multiple_pads(fpga_pads, ARRAY_SIZE(fpga_pads)); 172 gpio_direction_output(NOVENA_FPGA_RESET_N_GPIO, 0); 173 } 174 175 /* 176 * GPIO Button 177 */ 178 static iomux_v3_cfg_t button_pads[] = { 179 /* Debug */ 180 MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), 181 }; 182 183 static void novena_spl_setup_iomux_buttons(void) 184 { 185 imx_iomux_v3_setup_multiple_pads(button_pads, ARRAY_SIZE(button_pads)); 186 } 187 188 /* 189 * I2C 190 */ 191 /* 192 * I2C1: 193 * 0x1d ... MMA7455L 194 * 0x30 ... SO-DIMM temp sensor 195 * 0x44 ... STMPE610 196 * 0x50 ... SO-DIMM ID 197 */ 198 struct i2c_pads_info i2c_pad_info0 = { 199 .scl = { 200 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, 201 .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC, 202 .gp = IMX_GPIO_NR(3, 21) 203 }, 204 .sda = { 205 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, 206 .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC, 207 .gp = IMX_GPIO_NR(3, 28) 208 } 209 }; 210 211 /* 212 * I2C2: 213 * 0x08 ... PMIC 214 * 0x3a ... HDMI DCC 215 * 0x50 ... HDMI DCC 216 */ 217 static struct i2c_pads_info i2c_pad_info1 = { 218 .scl = { 219 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC, 220 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, 221 .gp = IMX_GPIO_NR(2, 30) 222 }, 223 .sda = { 224 .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC, 225 .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC, 226 .gp = IMX_GPIO_NR(3, 16) 227 } 228 }; 229 230 /* 231 * I2C3: 232 * 0x11 ... ES8283 233 * 0x50 ... LCD EDID 234 * 0x56 ... EEPROM 235 */ 236 static struct i2c_pads_info i2c_pad_info2 = { 237 .scl = { 238 .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC, 239 .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC, 240 .gp = IMX_GPIO_NR(3, 17) 241 }, 242 .sda = { 243 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, 244 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, 245 .gp = IMX_GPIO_NR(3, 18) 246 } 247 }; 248 249 static void novena_spl_setup_iomux_i2c(void) 250 { 251 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); 252 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 253 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); 254 } 255 256 /* 257 * PCI express 258 */ 259 #ifdef CONFIG_CMD_PCI 260 static iomux_v3_cfg_t pcie_pads[] = { 261 /* "Reset" pin */ 262 MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), 263 /* "Power on" pin */ 264 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), 265 /* "Wake up" pin (input) */ 266 MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), 267 /* "Disable endpoint" (rfkill) pin */ 268 MX6_PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), 269 }; 270 271 static void novena_spl_setup_iomux_pcie(void) 272 { 273 imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); 274 275 /* Ensure PCIe is powered down */ 276 gpio_direction_output(NOVENA_PCIE_POWER_ON_GPIO, 0); 277 278 /* Put the card into reset */ 279 gpio_direction_output(NOVENA_PCIE_RESET_GPIO, 0); 280 281 /* Input signal to wake system from mPCIe card */ 282 gpio_direction_input(NOVENA_PCIE_WAKE_UP_GPIO); 283 284 /* Drive RFKILL high, to ensure the radio is turned on */ 285 gpio_direction_output(NOVENA_PCIE_DISABLE_GPIO, 1); 286 } 287 #else 288 static inline void novena_spl_setup_iomux_pcie(void) {} 289 #endif 290 291 /* 292 * SDHC 293 */ 294 static iomux_v3_cfg_t usdhc2_pads[] = { 295 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 296 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 297 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 298 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 299 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 300 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 301 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */ 302 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 303 }; 304 305 static iomux_v3_cfg_t usdhc3_pads[] = { 306 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 307 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 308 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 309 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 310 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 311 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 312 }; 313 314 static void novena_spl_setup_iomux_sdhc(void) 315 { 316 imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 317 imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 318 319 /* Big SD write-protect and card-detect */ 320 gpio_direction_input(IMX_GPIO_NR(1, 2)); 321 gpio_direction_input(IMX_GPIO_NR(1, 4)); 322 } 323 324 /* 325 * SPI 326 */ 327 #ifdef CONFIG_MXC_SPI 328 static iomux_v3_cfg_t ecspi3_pads[] = { 329 /* SS1 */ 330 MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), 331 MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), 332 MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), 333 MX6_PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(SPI_PAD_CTRL), 334 MX6_PAD_DISP0_DAT4__GPIO4_IO25 | MUX_PAD_CTRL(SPI_PAD_CTRL), 335 MX6_PAD_DISP0_DAT5__GPIO4_IO26 | MUX_PAD_CTRL(SPI_PAD_CTRL), 336 MX6_PAD_DISP0_DAT7__ECSPI3_RDY | MUX_PAD_CTRL(SPI_PAD_CTRL), 337 }; 338 339 static void novena_spl_setup_iomux_spi(void) 340 { 341 imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads)); 342 /* De-assert the nCS */ 343 gpio_direction_output(MX6_PAD_DISP0_DAT3__GPIO4_IO24, 1); 344 gpio_direction_output(MX6_PAD_DISP0_DAT4__GPIO4_IO25, 1); 345 gpio_direction_output(MX6_PAD_DISP0_DAT5__GPIO4_IO26, 1); 346 } 347 #else 348 static void novena_spl_setup_iomux_spi(void) {} 349 #endif 350 351 /* 352 * UART 353 */ 354 static iomux_v3_cfg_t const uart2_pads[] = { 355 MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 356 MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 357 }; 358 359 static iomux_v3_cfg_t const uart3_pads[] = { 360 MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 361 MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 362 }; 363 364 static iomux_v3_cfg_t const uart4_pads[] = { 365 MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 366 MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 367 MX6_PAD_CSI0_DAT16__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), 368 MX6_PAD_CSI0_DAT17__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), 369 370 }; 371 372 static void novena_spl_setup_iomux_uart(void) 373 { 374 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); 375 imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); 376 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); 377 } 378 379 /* 380 * Video 381 */ 382 #ifdef CONFIG_VIDEO 383 static iomux_v3_cfg_t hdmi_pads[] = { 384 /* "Ghost HPD" pin */ 385 MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), 386 387 /* LCD_PWR_CTL */ 388 MX6_PAD_CSI0_DAT10__GPIO5_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), 389 /* LCD_BL_ON */ 390 MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), 391 /* GPIO_PWM1 */ 392 MX6_PAD_DISP0_DAT8__GPIO4_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), 393 }; 394 395 static void novena_spl_setup_iomux_video(void) 396 { 397 imx_iomux_v3_setup_multiple_pads(hdmi_pads, ARRAY_SIZE(hdmi_pads)); 398 gpio_direction_input(NOVENA_HDMI_GHOST_HPD); 399 } 400 #else 401 static inline void novena_spl_setup_iomux_video(void) {} 402 #endif 403 404 /* 405 * SPL boots from uSDHC card 406 */ 407 #ifdef CONFIG_FSL_ESDHC 408 static struct fsl_esdhc_cfg usdhc_cfg = { 409 USDHC3_BASE_ADDR, 0, 4 410 }; 411 412 int board_mmc_getcd(struct mmc *mmc) 413 { 414 /* There is no CD for a microSD card, assume always present. */ 415 return 1; 416 } 417 418 int board_mmc_init(bd_t *bis) 419 { 420 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 421 return fsl_esdhc_initialize(bis, &usdhc_cfg); 422 } 423 #endif 424 425 /* Configure MX6Q/DUAL mmdc DDR io registers */ 426 static struct mx6dq_iomux_ddr_regs novena_ddr_ioregs = { 427 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ 428 .dram_sdclk_0 = 0x00020038, 429 .dram_sdclk_1 = 0x00020038, 430 .dram_cas = 0x00000038, 431 .dram_ras = 0x00000038, 432 .dram_reset = 0x00000038, 433 /* SDCKE[0:1]: 100k pull-up */ 434 .dram_sdcke0 = 0x00000038, 435 .dram_sdcke1 = 0x00000038, 436 /* SDBA2: pull-up disabled */ 437 .dram_sdba2 = 0x00000000, 438 /* SDODT[0:1]: 100k pull-up, 40 ohm */ 439 .dram_sdodt0 = 0x00000038, 440 .dram_sdodt1 = 0x00000038, 441 /* SDQS[0:7]: Differential input, 40 ohm */ 442 .dram_sdqs0 = 0x00000038, 443 .dram_sdqs1 = 0x00000038, 444 .dram_sdqs2 = 0x00000038, 445 .dram_sdqs3 = 0x00000038, 446 .dram_sdqs4 = 0x00000038, 447 .dram_sdqs5 = 0x00000038, 448 .dram_sdqs6 = 0x00000038, 449 .dram_sdqs7 = 0x00000038, 450 451 /* DQM[0:7]: Differential input, 40 ohm */ 452 .dram_dqm0 = 0x00000038, 453 .dram_dqm1 = 0x00000038, 454 .dram_dqm2 = 0x00000038, 455 .dram_dqm3 = 0x00000038, 456 .dram_dqm4 = 0x00000038, 457 .dram_dqm5 = 0x00000038, 458 .dram_dqm6 = 0x00000038, 459 .dram_dqm7 = 0x00000038, 460 }; 461 462 /* Configure MX6Q/DUAL mmdc GRP io registers */ 463 static struct mx6dq_iomux_grp_regs novena_grp_ioregs = { 464 /* DDR3 */ 465 .grp_ddr_type = 0x000c0000, 466 .grp_ddrmode_ctl = 0x00020000, 467 /* Disable DDR pullups */ 468 .grp_ddrpke = 0x00000000, 469 /* ADDR[00:16], SDBA[0:1]: 40 ohm */ 470 .grp_addds = 0x00000038, 471 /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ 472 .grp_ctlds = 0x00000038, 473 /* DATA[00:63]: Differential input, 40 ohm */ 474 .grp_ddrmode = 0x00020000, 475 .grp_b0ds = 0x00000038, 476 .grp_b1ds = 0x00000038, 477 .grp_b2ds = 0x00000038, 478 .grp_b3ds = 0x00000038, 479 .grp_b4ds = 0x00000038, 480 .grp_b5ds = 0x00000038, 481 .grp_b6ds = 0x00000038, 482 .grp_b7ds = 0x00000038, 483 }; 484 485 static struct mx6_mmdc_calibration novena_mmdc_calib = { 486 /* write leveling calibration determine */ 487 .p0_mpwldectrl0 = 0x00420048, 488 .p0_mpwldectrl1 = 0x006f0059, 489 .p1_mpwldectrl0 = 0x005a0104, 490 .p1_mpwldectrl1 = 0x01070113, 491 /* Read DQS Gating calibration */ 492 .p0_mpdgctrl0 = 0x437c040b, 493 .p0_mpdgctrl1 = 0x0413040e, 494 .p1_mpdgctrl0 = 0x444f0446, 495 .p1_mpdgctrl1 = 0x044d0422, 496 /* Read Calibration: DQS delay relative to DQ read access */ 497 .p0_mprddlctl = 0x4c424249, 498 .p1_mprddlctl = 0x4e48414f, 499 /* Write Calibration: DQ/DM delay relative to DQS write access */ 500 .p0_mpwrdlctl = 0x42414641, 501 .p1_mpwrdlctl = 0x46374b43, 502 }; 503 504 static struct mx6_ddr_sysinfo novena_ddr_info = { 505 /* Width of data bus: 0=16, 1=32, 2=64 */ 506 .dsize = 2, 507 /* Config for full 4GB range so that get_mem_size() works */ 508 .cs_density = 32, /* 32Gb per CS */ 509 /* Single chip select */ 510 .ncs = 1, 511 .cs1_mirror = 0, 512 .rtt_wr = 0, /* RTT_Wr = RZQ/4 */ 513 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ 514 .walat = 0, /* Write additional latency */ 515 .ralat = 5, /* Read additional latency */ 516 .mif3_mode = 3, /* Command prediction working mode */ 517 .bi_on = 1, /* Bank interleaving enabled */ 518 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 519 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 520 .refsel = 1, /* Refresh cycles at 32KHz */ 521 .refr = 7, /* 8 refresh commands per refresh cycle */ 522 }; 523 524 static struct mx6_ddr3_cfg elpida_4gib_1600 = { 525 .mem_speed = 1600, 526 .density = 4, 527 .width = 64, 528 .banks = 8, 529 .rowaddr = 16, 530 .coladdr = 10, 531 .pagesz = 2, 532 .trcd = 1375, 533 .trcmin = 4875, 534 .trasmin = 3500, 535 }; 536 537 static void ccgr_init(void) 538 { 539 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 540 541 writel(0x00C03F3F, &ccm->CCGR0); 542 writel(0x0030FC03, &ccm->CCGR1); 543 writel(0x0FFFC000, &ccm->CCGR2); 544 writel(0x3FF00000, &ccm->CCGR3); 545 writel(0xFFFFF300, &ccm->CCGR4); 546 writel(0x0F0000C3, &ccm->CCGR5); 547 writel(0x000003FF, &ccm->CCGR6); 548 } 549 550 /* 551 * called from C runtime startup code (arch/arm/lib/crt0.S:_main) 552 * - we have a stack and a place to store GD, both in SRAM 553 * - no variable global data is available 554 */ 555 void board_init_f(ulong dummy) 556 { 557 /* setup AIPS and disable watchdog */ 558 arch_cpu_init(); 559 560 ccgr_init(); 561 gpr_init(); 562 563 /* setup GP timer */ 564 timer_init(); 565 566 #ifdef CONFIG_BOARD_POSTCLK_INIT 567 board_postclk_init(); 568 #endif 569 #ifdef CONFIG_FSL_ESDHC 570 get_clocks(); 571 #endif 572 573 /* Setup IOMUX and configure basics. */ 574 novena_spl_setup_iomux_audio(); 575 novena_spl_setup_iomux_buttons(); 576 novena_spl_setup_iomux_enet(); 577 novena_spl_setup_iomux_fpga(); 578 novena_spl_setup_iomux_i2c(); 579 novena_spl_setup_iomux_pcie(); 580 novena_spl_setup_iomux_sdhc(); 581 novena_spl_setup_iomux_spi(); 582 novena_spl_setup_iomux_uart(); 583 novena_spl_setup_iomux_video(); 584 585 /* UART clocks enabled and gd valid - init serial console */ 586 preloader_console_init(); 587 588 /* Start the DDR DRAM */ 589 mx6dq_dram_iocfg(64, &novena_ddr_ioregs, &novena_grp_ioregs); 590 mx6_dram_cfg(&novena_ddr_info, &novena_mmdc_calib, &elpida_4gib_1600); 591 592 /* Perform DDR DRAM calibration */ 593 udelay(100); 594 mmdc_do_write_level_calibration(&novena_ddr_info); 595 mmdc_do_dqs_calibration(&novena_ddr_info); 596 } 597