1 /* 2 * Novena SPL 3 * 4 * Copyright (C) 2014 Marek Vasut <marex@denx.de> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/io.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/iomux.h> 13 #include <asm/arch/mx6-ddr.h> 14 #include <asm/arch/mx6-pins.h> 15 #include <asm/arch/sys_proto.h> 16 #include <asm/gpio.h> 17 #include <asm/imx-common/boot_mode.h> 18 #include <asm/imx-common/iomux-v3.h> 19 #include <asm/imx-common/mxc_i2c.h> 20 #include <asm/arch/crm_regs.h> 21 #include <i2c.h> 22 #include <mmc.h> 23 #include <fsl_esdhc.h> 24 #include <spl.h> 25 26 #include <asm/arch/mx6-ddr.h> 27 28 DECLARE_GLOBAL_DATA_PTR; 29 30 #define UART_PAD_CTRL \ 31 (PAD_CTL_PKE | PAD_CTL_PUE | \ 32 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 33 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 34 35 #define USDHC_PAD_CTRL \ 36 (PAD_CTL_PKE | PAD_CTL_PUE | \ 37 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ 38 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 39 40 #define ENET_PAD_CTRL \ 41 (PAD_CTL_PKE | PAD_CTL_PUE | \ 42 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 43 PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 44 45 #define ENET_PHY_CFG_PAD_CTRL \ 46 (PAD_CTL_PKE | PAD_CTL_PUE | \ 47 PAD_CTL_PUS_22K_UP | PAD_CTL_HYS) 48 49 #define RGMII_PAD_CTRL \ 50 (PAD_CTL_PKE | PAD_CTL_PUE | \ 51 PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 52 53 #define SPI_PAD_CTRL \ 54 (PAD_CTL_HYS | \ 55 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ 56 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 57 58 #define I2C_PAD_CTRL \ 59 (PAD_CTL_PKE | PAD_CTL_PUE | \ 60 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ 61 PAD_CTL_DSE_240ohm | PAD_CTL_HYS | \ 62 PAD_CTL_ODE) 63 64 #define BUTTON_PAD_CTRL \ 65 (PAD_CTL_PKE | PAD_CTL_PUE | \ 66 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 67 PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 68 69 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 70 71 #define NOVENA_AUDIO_PWRON IMX_GPIO_NR(5, 17) 72 #define NOVENA_FPGA_RESET_N_GPIO IMX_GPIO_NR(5, 7) 73 #define NOVENA_HDMI_GHOST_HPD IMX_GPIO_NR(5, 4) 74 #define NOVENA_PCIE_RESET_GPIO IMX_GPIO_NR(3, 29) 75 #define NOVENA_PCIE_POWER_ON_GPIO IMX_GPIO_NR(7, 12) 76 #define NOVENA_PCIE_WAKE_UP_GPIO IMX_GPIO_NR(3, 22) 77 #define NOVENA_PCIE_DISABLE_GPIO IMX_GPIO_NR(2, 16) 78 79 /* 80 * Audio 81 */ 82 static iomux_v3_cfg_t audio_pads[] = { 83 /* AUD_PWRON */ 84 MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), 85 }; 86 87 static void novena_spl_setup_iomux_audio(void) 88 { 89 imx_iomux_v3_setup_multiple_pads(audio_pads, ARRAY_SIZE(audio_pads)); 90 gpio_direction_output(NOVENA_AUDIO_PWRON, 1); 91 } 92 93 /* 94 * ENET 95 */ 96 static iomux_v3_cfg_t enet_pads1[] = { 97 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 98 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 99 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(RGMII_PAD_CTRL), 100 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(RGMII_PAD_CTRL), 101 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(RGMII_PAD_CTRL), 102 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(RGMII_PAD_CTRL), 103 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(RGMII_PAD_CTRL), 104 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(RGMII_PAD_CTRL), 105 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 106 107 /* pin 35, PHY_AD2 */ 108 MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL), 109 /* pin 32, MODE0 */ 110 MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL), 111 /* pin 31, MODE1 */ 112 MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL), 113 /* pin 28, MODE2 */ 114 MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL), 115 /* pin 27, MODE3 */ 116 MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL), 117 /* pin 33, CLK125_EN */ 118 MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL), 119 120 /* pin 42 PHY nRST */ 121 MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), 122 }; 123 124 static iomux_v3_cfg_t enet_pads2[] = { 125 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(RGMII_PAD_CTRL), 126 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(RGMII_PAD_CTRL), 127 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(RGMII_PAD_CTRL), 128 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(RGMII_PAD_CTRL), 129 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(RGMII_PAD_CTRL), 130 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(RGMII_PAD_CTRL), 131 }; 132 133 static void novena_spl_setup_iomux_enet(void) 134 { 135 imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); 136 137 /* Assert Ethernet PHY nRST */ 138 gpio_direction_output(IMX_GPIO_NR(3, 23), 0); 139 140 /* 141 * Use imx6 internal pull-ups to drive PHY mode pins during PHY reset 142 * de-assertion. The intention is to use weak signal drivers (pull-ups) 143 * to prevent the conflict between PHY pins becoming outputs after 144 * reset and imx6 still driving the pins. The issue is described in PHY 145 * datasheet, p.14 146 */ 147 gpio_direction_input(IMX_GPIO_NR(6, 30)); /* PHY_AD2 = 1 */ 148 gpio_direction_input(IMX_GPIO_NR(6, 25)); /* MODE0 = 1 */ 149 gpio_direction_input(IMX_GPIO_NR(6, 27)); /* MODE1 = 1 */ 150 gpio_direction_input(IMX_GPIO_NR(6, 28)); /* MODE2 = 1 */ 151 gpio_direction_input(IMX_GPIO_NR(6, 29)); /* MODE3 = 1 */ 152 gpio_direction_input(IMX_GPIO_NR(6, 24)); /* CLK125_EN = 1 */ 153 154 /* Following reset timing (p.53, fig.8 from the PHY datasheet) */ 155 mdelay(10); 156 157 /* De-assert Ethernet PHY nRST */ 158 gpio_set_value(IMX_GPIO_NR(3, 23), 1); 159 160 /* PHY is now configured, connect FEC to the pads */ 161 imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); 162 163 /* 164 * PHY datasheet recommends on p.53 to wait at least 100us after reset 165 * before using MII, so we enforce the delay here 166 */ 167 udelay(100); 168 } 169 170 /* 171 * FPGA 172 */ 173 static iomux_v3_cfg_t fpga_pads[] = { 174 /* FPGA_RESET_N */ 175 MX6_PAD_DISP0_DAT13__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), 176 }; 177 178 static void novena_spl_setup_iomux_fpga(void) 179 { 180 imx_iomux_v3_setup_multiple_pads(fpga_pads, ARRAY_SIZE(fpga_pads)); 181 gpio_direction_output(NOVENA_FPGA_RESET_N_GPIO, 0); 182 } 183 184 /* 185 * GPIO Button 186 */ 187 static iomux_v3_cfg_t button_pads[] = { 188 /* Debug */ 189 MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), 190 }; 191 192 static void novena_spl_setup_iomux_buttons(void) 193 { 194 imx_iomux_v3_setup_multiple_pads(button_pads, ARRAY_SIZE(button_pads)); 195 } 196 197 /* 198 * I2C 199 */ 200 /* 201 * I2C1: 202 * 0x1d ... MMA7455L 203 * 0x30 ... SO-DIMM temp sensor 204 * 0x44 ... STMPE610 205 * 0x50 ... SO-DIMM ID 206 */ 207 struct i2c_pads_info i2c_pad_info0 = { 208 .scl = { 209 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, 210 .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC, 211 .gp = IMX_GPIO_NR(3, 21) 212 }, 213 .sda = { 214 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, 215 .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC, 216 .gp = IMX_GPIO_NR(3, 28) 217 } 218 }; 219 220 /* 221 * I2C2: 222 * 0x08 ... PMIC 223 * 0x3a ... HDMI DCC 224 * 0x50 ... HDMI DCC 225 */ 226 static struct i2c_pads_info i2c_pad_info1 = { 227 .scl = { 228 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC, 229 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, 230 .gp = IMX_GPIO_NR(2, 30) 231 }, 232 .sda = { 233 .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC, 234 .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC, 235 .gp = IMX_GPIO_NR(3, 16) 236 } 237 }; 238 239 /* 240 * I2C3: 241 * 0x11 ... ES8283 242 * 0x50 ... LCD EDID 243 * 0x56 ... EEPROM 244 */ 245 static struct i2c_pads_info i2c_pad_info2 = { 246 .scl = { 247 .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC, 248 .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC, 249 .gp = IMX_GPIO_NR(3, 17) 250 }, 251 .sda = { 252 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, 253 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, 254 .gp = IMX_GPIO_NR(3, 18) 255 } 256 }; 257 258 static void novena_spl_setup_iomux_i2c(void) 259 { 260 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); 261 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 262 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); 263 } 264 265 /* 266 * PCI express 267 */ 268 #ifdef CONFIG_CMD_PCI 269 static iomux_v3_cfg_t pcie_pads[] = { 270 /* "Reset" pin */ 271 MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), 272 /* "Power on" pin */ 273 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), 274 /* "Wake up" pin (input) */ 275 MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), 276 /* "Disable endpoint" (rfkill) pin */ 277 MX6_PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), 278 }; 279 280 static void novena_spl_setup_iomux_pcie(void) 281 { 282 imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); 283 284 /* Ensure PCIe is powered down */ 285 gpio_direction_output(NOVENA_PCIE_POWER_ON_GPIO, 0); 286 287 /* Put the card into reset */ 288 gpio_direction_output(NOVENA_PCIE_RESET_GPIO, 0); 289 290 /* Input signal to wake system from mPCIe card */ 291 gpio_direction_input(NOVENA_PCIE_WAKE_UP_GPIO); 292 293 /* Drive RFKILL high, to ensure the radio is turned on */ 294 gpio_direction_output(NOVENA_PCIE_DISABLE_GPIO, 1); 295 } 296 #else 297 static inline void novena_spl_setup_iomux_pcie(void) {} 298 #endif 299 300 /* 301 * SDHC 302 */ 303 static iomux_v3_cfg_t usdhc2_pads[] = { 304 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 305 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 306 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 307 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 308 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 309 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 310 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */ 311 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 312 }; 313 314 static iomux_v3_cfg_t usdhc3_pads[] = { 315 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 316 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 317 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 318 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 319 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 320 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 321 }; 322 323 static void novena_spl_setup_iomux_sdhc(void) 324 { 325 imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 326 imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 327 328 /* Big SD write-protect and card-detect */ 329 gpio_direction_input(IMX_GPIO_NR(1, 2)); 330 gpio_direction_input(IMX_GPIO_NR(1, 4)); 331 } 332 333 /* 334 * SPI 335 */ 336 #ifdef CONFIG_MXC_SPI 337 static iomux_v3_cfg_t ecspi3_pads[] = { 338 /* SS1 */ 339 MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), 340 MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), 341 MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), 342 MX6_PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(SPI_PAD_CTRL), 343 MX6_PAD_DISP0_DAT4__GPIO4_IO25 | MUX_PAD_CTRL(SPI_PAD_CTRL), 344 MX6_PAD_DISP0_DAT5__GPIO4_IO26 | MUX_PAD_CTRL(SPI_PAD_CTRL), 345 MX6_PAD_DISP0_DAT7__ECSPI3_RDY | MUX_PAD_CTRL(SPI_PAD_CTRL), 346 }; 347 348 static void novena_spl_setup_iomux_spi(void) 349 { 350 imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads)); 351 /* De-assert the nCS */ 352 gpio_direction_output(MX6_PAD_DISP0_DAT3__GPIO4_IO24, 1); 353 gpio_direction_output(MX6_PAD_DISP0_DAT4__GPIO4_IO25, 1); 354 gpio_direction_output(MX6_PAD_DISP0_DAT5__GPIO4_IO26, 1); 355 } 356 #else 357 static void novena_spl_setup_iomux_spi(void) {} 358 #endif 359 360 /* 361 * UART 362 */ 363 static iomux_v3_cfg_t const uart2_pads[] = { 364 MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 365 MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 366 }; 367 368 static iomux_v3_cfg_t const uart3_pads[] = { 369 MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 370 MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 371 }; 372 373 static iomux_v3_cfg_t const uart4_pads[] = { 374 MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 375 MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 376 MX6_PAD_CSI0_DAT16__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), 377 MX6_PAD_CSI0_DAT17__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), 378 379 }; 380 381 static void novena_spl_setup_iomux_uart(void) 382 { 383 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); 384 imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); 385 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); 386 } 387 388 /* 389 * Video 390 */ 391 #ifdef CONFIG_VIDEO 392 static iomux_v3_cfg_t hdmi_pads[] = { 393 /* "Ghost HPD" pin */ 394 MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), 395 }; 396 397 static void novena_spl_setup_iomux_video(void) 398 { 399 imx_iomux_v3_setup_multiple_pads(hdmi_pads, ARRAY_SIZE(hdmi_pads)); 400 gpio_direction_input(NOVENA_HDMI_GHOST_HPD); 401 } 402 #else 403 static inline void novena_spl_setup_iomux_video(void) {} 404 #endif 405 406 /* 407 * SPL boots from uSDHC card 408 */ 409 #ifdef CONFIG_FSL_ESDHC 410 static struct fsl_esdhc_cfg usdhc_cfg = { 411 USDHC3_BASE_ADDR, 0, 4 412 }; 413 414 int board_mmc_getcd(struct mmc *mmc) 415 { 416 /* There is no CD for a microSD card, assume always present. */ 417 return 1; 418 } 419 420 int board_mmc_init(bd_t *bis) 421 { 422 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 423 return fsl_esdhc_initialize(bis, &usdhc_cfg); 424 } 425 #endif 426 427 /* Configure MX6Q/DUAL mmdc DDR io registers */ 428 static struct mx6dq_iomux_ddr_regs novena_ddr_ioregs = { 429 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ 430 .dram_sdclk_0 = 0x00020038, 431 .dram_sdclk_1 = 0x00020038, 432 .dram_cas = 0x00000038, 433 .dram_ras = 0x00000038, 434 .dram_reset = 0x00000038, 435 /* SDCKE[0:1]: 100k pull-up */ 436 .dram_sdcke0 = 0x00003000, 437 .dram_sdcke1 = 0x00003000, 438 /* SDBA2: pull-up disabled */ 439 .dram_sdba2 = 0x00000000, 440 /* SDODT[0:1]: 100k pull-up, 40 ohm */ 441 .dram_sdodt0 = 0x00000038, 442 .dram_sdodt1 = 0x00000038, 443 /* SDQS[0:7]: Differential input, 40 ohm */ 444 .dram_sdqs0 = 0x00000038, 445 .dram_sdqs1 = 0x00000038, 446 .dram_sdqs2 = 0x00000038, 447 .dram_sdqs3 = 0x00000038, 448 .dram_sdqs4 = 0x00000038, 449 .dram_sdqs5 = 0x00000038, 450 .dram_sdqs6 = 0x00000038, 451 .dram_sdqs7 = 0x00000038, 452 453 /* DQM[0:7]: Differential input, 40 ohm */ 454 .dram_dqm0 = 0x00000038, 455 .dram_dqm1 = 0x00000038, 456 .dram_dqm2 = 0x00000038, 457 .dram_dqm3 = 0x00000038, 458 .dram_dqm4 = 0x00000038, 459 .dram_dqm5 = 0x00000038, 460 .dram_dqm6 = 0x00000038, 461 .dram_dqm7 = 0x00000038, 462 }; 463 464 /* Configure MX6Q/DUAL mmdc GRP io registers */ 465 static struct mx6dq_iomux_grp_regs novena_grp_ioregs = { 466 /* DDR3 */ 467 .grp_ddr_type = 0x000c0000, 468 .grp_ddrmode_ctl = 0x00020000, 469 /* Disable DDR pullups */ 470 .grp_ddrpke = 0x00000000, 471 /* ADDR[00:16], SDBA[0:1]: 40 ohm */ 472 .grp_addds = 0x00000038, 473 /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ 474 .grp_ctlds = 0x00000038, 475 /* DATA[00:63]: Differential input, 40 ohm */ 476 .grp_ddrmode = 0x00020000, 477 .grp_b0ds = 0x00000038, 478 .grp_b1ds = 0x00000038, 479 .grp_b2ds = 0x00000038, 480 .grp_b3ds = 0x00000038, 481 .grp_b4ds = 0x00000038, 482 .grp_b5ds = 0x00000038, 483 .grp_b6ds = 0x00000038, 484 .grp_b7ds = 0x00000038, 485 }; 486 487 static struct mx6_mmdc_calibration novena_mmdc_calib = { 488 /* write leveling calibration determine */ 489 .p0_mpwldectrl0 = 0x00420048, 490 .p0_mpwldectrl1 = 0x006f0059, 491 .p1_mpwldectrl0 = 0x005a0104, 492 .p1_mpwldectrl1 = 0x01070113, 493 /* Read DQS Gating calibration */ 494 .p0_mpdgctrl0 = 0x437c040b, 495 .p0_mpdgctrl1 = 0x0413040e, 496 .p1_mpdgctrl0 = 0x444f0446, 497 .p1_mpdgctrl1 = 0x044d0422, 498 /* Read Calibration: DQS delay relative to DQ read access */ 499 .p0_mprddlctl = 0x4c424249, 500 .p1_mprddlctl = 0x4e48414f, 501 /* Write Calibration: DQ/DM delay relative to DQS write access */ 502 .p0_mpwrdlctl = 0x42414641, 503 .p1_mpwrdlctl = 0x46374b43, 504 }; 505 506 static struct mx6_ddr_sysinfo novena_ddr_info = { 507 /* Width of data bus: 0=16, 1=32, 2=64 */ 508 .dsize = 2, 509 /* Config for full 4GB range so that get_mem_size() works */ 510 .cs_density = 32, /* 32Gb per CS */ 511 /* Single chip select */ 512 .ncs = 1, 513 .cs1_mirror = 0, 514 .rtt_wr = 1, /* RTT_Wr = RZQ/4 */ 515 .rtt_nom = 2, /* RTT_Nom = RZQ/2 */ 516 .walat = 3, /* Write additional latency */ 517 .ralat = 7, /* Read additional latency */ 518 .mif3_mode = 3, /* Command prediction working mode */ 519 .bi_on = 1, /* Bank interleaving enabled */ 520 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 521 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 522 }; 523 524 static struct mx6_ddr3_cfg elpida_4gib_1600 = { 525 .mem_speed = 1600, 526 .density = 4, 527 .width = 64, 528 .banks = 8, 529 .rowaddr = 16, 530 .coladdr = 10, 531 .pagesz = 2, 532 .trcd = 1300, 533 .trcmin = 4900, 534 .trasmin = 3590, 535 }; 536 537 static void ccgr_init(void) 538 { 539 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 540 541 writel(0x00C03F3F, &ccm->CCGR0); 542 writel(0x0030FC03, &ccm->CCGR1); 543 writel(0x0FFFC000, &ccm->CCGR2); 544 writel(0x3FF00000, &ccm->CCGR3); 545 writel(0xFFFFF300, &ccm->CCGR4); 546 writel(0x0F0000C3, &ccm->CCGR5); 547 writel(0x000003FF, &ccm->CCGR6); 548 } 549 550 static void gpr_init(void) 551 { 552 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 553 554 /* enable AXI cache for VDOA/VPU/IPU */ 555 writel(0xF00000CF, &iomux->gpr[4]); 556 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ 557 writel(0x007F007F, &iomux->gpr[6]); 558 writel(0x007F007F, &iomux->gpr[7]); 559 } 560 561 /* 562 * called from C runtime startup code (arch/arm/lib/crt0.S:_main) 563 * - we have a stack and a place to store GD, both in SRAM 564 * - no variable global data is available 565 */ 566 void board_init_f(ulong dummy) 567 { 568 /* setup AIPS and disable watchdog */ 569 arch_cpu_init(); 570 571 ccgr_init(); 572 gpr_init(); 573 574 /* setup GP timer */ 575 timer_init(); 576 577 #ifdef CONFIG_BOARD_POSTCLK_INIT 578 board_postclk_init(); 579 #endif 580 #ifdef CONFIG_FSL_ESDHC 581 get_clocks(); 582 #endif 583 584 /* Setup IOMUX and configure basics. */ 585 novena_spl_setup_iomux_audio(); 586 novena_spl_setup_iomux_buttons(); 587 novena_spl_setup_iomux_enet(); 588 novena_spl_setup_iomux_fpga(); 589 novena_spl_setup_iomux_i2c(); 590 novena_spl_setup_iomux_pcie(); 591 novena_spl_setup_iomux_sdhc(); 592 novena_spl_setup_iomux_spi(); 593 novena_spl_setup_iomux_uart(); 594 novena_spl_setup_iomux_video(); 595 596 /* UART clocks enabled and gd valid - init serial console */ 597 preloader_console_init(); 598 599 /* Start the DDR DRAM */ 600 mx6dq_dram_iocfg(64, &novena_ddr_ioregs, &novena_grp_ioregs); 601 mx6_dram_cfg(&novena_ddr_info, &novena_mmdc_calib, &elpida_4gib_1600); 602 603 /* Clear the BSS. */ 604 memset(__bss_start, 0, __bss_end - __bss_start); 605 606 /* load/boot image from boot device */ 607 board_init_r(NULL, 0); 608 } 609 610 void reset_cpu(ulong addr) 611 { 612 } 613