1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2018 Dennis Gilmore <dgilmore@redhat.com> 4 * based on board/solidrun/clearfog/clearfog.c 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <miiphy.h> 10 #include <netdev.h> 11 #include <asm/io.h> 12 #include <asm/arch/cpu.h> 13 #include <asm/arch/soc.h> 14 15 #include "../drivers/ddr/marvell/a38x/ddr3_init.h" 16 #include <../serdes/a38x/high_speed_env_spec.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 #define ETH_PHY_CTRL_REG 0 21 #define ETH_PHY_CTRL_POWER_DOWN_BIT 11 22 #define ETH_PHY_CTRL_POWER_DOWN_MASK BIT(ETH_PHY_CTRL_POWER_DOWN_BIT) 23 24 /* 25 * Those values and defines are taken from the Marvell U-Boot version 26 * "u-boot-2013.01-15t1-helios4" as well as the upstream config for clearfog 27 */ 28 #define BOARD_GPP_OUT_ENA_LOW 0xffffffff 29 #define BOARD_GPP_OUT_ENA_MID 0xffffffff 30 31 #define BOARD_GPP_OUT_VAL_LOW 0x0 32 #define BOARD_GPP_OUT_VAL_MID 0x0 33 #define BOARD_GPP_POL_LOW 0x0 34 #define BOARD_GPP_POL_MID 0x0 35 36 static struct serdes_map board_serdes_map[] = { 37 {SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 38 {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 39 {SATA1, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 40 {SATA3, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 41 {SATA2, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 42 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 43 }; 44 45 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count) 46 { 47 *serdes_map_array = board_serdes_map; 48 *count = ARRAY_SIZE(board_serdes_map); 49 return 0; 50 } 51 52 /* 53 * Define the DDR layout / topology here in the board file. This will 54 * be used by the DDR3 init code in the SPL U-Boot version to configure 55 * the DDR3 controller. 56 */ 57 static struct mv_ddr_topology_map board_topology_map = { 58 DEBUG_LEVEL_ERROR, 59 0x1, /* active interfaces */ 60 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */ 61 { { { {0x1, 0, 0, 0}, 62 {0x1, 0, 0, 0}, 63 {0x1, 0, 0, 0}, 64 {0x1, 0, 0, 0}, 65 {0x1, 0, 0, 0} }, 66 SPEED_BIN_DDR_1600K, /* speed_bin */ 67 MV_DDR_DEV_WIDTH_16BIT, /* memory_width */ 68 MV_DDR_DIE_CAP_8GBIT, /* mem_size */ 69 MV_DDR_FREQ_800, /* frequency */ 70 0, 0, /* cas_wl cas_l */ 71 MV_DDR_TEMP_LOW, /* temperature */ 72 MV_DDR_TIM_DEFAULT} }, /* timing */ 73 BUS_MASK_32BIT_ECC, /* Busses mask */ 74 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ 75 { {0} }, /* raw spd data */ 76 {0} /* timing parameters */ 77 }; 78 79 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) 80 { 81 /* Return the board topology as defined in the board code */ 82 return &board_topology_map; 83 } 84 85 int board_early_init_f(void) 86 { 87 /* Configure MPP */ 88 writel(0x11111111, MVEBU_MPP_BASE + 0x00); 89 writel(0x11111111, MVEBU_MPP_BASE + 0x04); 90 writel(0x10400011, MVEBU_MPP_BASE + 0x08); 91 writel(0x22043333, MVEBU_MPP_BASE + 0x0c); 92 writel(0x44400002, MVEBU_MPP_BASE + 0x10); 93 writel(0x41144004, MVEBU_MPP_BASE + 0x14); 94 writel(0x40333333, MVEBU_MPP_BASE + 0x18); 95 writel(0x00004444, MVEBU_MPP_BASE + 0x1c); 96 97 /* Set GPP Out value */ 98 writel(BOARD_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); 99 writel(BOARD_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); 100 101 /* Set GPP Polarity */ 102 writel(BOARD_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c); 103 writel(BOARD_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); 104 105 /* Set GPP Out Enable */ 106 writel(BOARD_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); 107 writel(BOARD_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); 108 109 return 0; 110 } 111 112 int board_init(void) 113 { 114 /* Address of boot parameters */ 115 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; 116 117 return 0; 118 } 119 120 int checkboard(void) 121 { 122 puts("Board: Helios4\n"); 123 124 return 0; 125 } 126 127 int board_eth_init(bd_t *bis) 128 { 129 cpu_eth_init(bis); /* Built in controller(s) come first */ 130 return pci_eth_init(bis); 131 } 132