1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 4 * (C) Copyright 2012 Renesas Solutions Corp. 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <asm/arch/sys_proto.h> 10 #include <asm/gpio.h> 11 #include <netdev.h> 12 #include <i2c.h> 13 14 DECLARE_GLOBAL_DATA_PTR; 15 16 #define CS0BCR_D (0x06C00400) 17 #define CS4BCR_D (0x16c90400) 18 #define CS0WCR_D (0x55062C42) 19 #define CS4WCR_D (0x1e071dc3) 20 21 #define CMNCR_BROMMD0 (1 << 21) 22 #define CMNCR_BROMMD1 (1 << 22) 23 #define CMNCR_BROMMD (CMNCR_BROMMD0|CMNCR_BROMMD1) 24 #define VCLKCR1_D (0x27) 25 26 #define SMSTPCR1_CMT0 (1 << 24) 27 #define SMSTPCR1_I2C0 (1 << 16) 28 #define SMSTPCR3_USB (1 << 22) 29 #define SMSTPCR3_I2C1 (1 << 23) 30 31 #define PORT32CR (0xE6051020) 32 #define PORT33CR (0xE6051021) 33 #define PORT34CR (0xE6051022) 34 #define PORT35CR (0xE6051023) 35 36 static int cmp_loop(u32 *addr, u32 data, u32 cmp) 37 { 38 int err = -1; 39 int timeout = 100; 40 u32 value; 41 42 while (timeout > 0) { 43 value = readl(addr); 44 if ((value & data) == cmp) { 45 err = 0; 46 break; 47 } 48 timeout--; 49 } 50 51 return err; 52 } 53 54 /* SBSC Init function */ 55 static void sbsc_init(struct sh73a0_sbsc *sbsc) 56 { 57 writel(readl(&sbsc->dllcnt0)|0x2, &sbsc->dllcnt0); 58 writel(0x5, &sbsc->sdgencnt); 59 cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); 60 61 writel(0xacc90159, &sbsc->sdcr0); 62 writel(0x00010059, &sbsc->sdcr1); 63 writel(0x50874114, &sbsc->sdwcrc0); 64 writel(0x33199b37, &sbsc->sdwcrc1); 65 writel(0x008f2313, &sbsc->sdwcrc2); 66 writel(0x31020707, &sbsc->sdwcr00); 67 writel(0x0017040a, &sbsc->sdwcr01); 68 writel(0x31020707, &sbsc->sdwcr10); 69 writel(0x0017040a, &sbsc->sdwcr11); 70 writel(0x055557ff, &sbsc->sddrvcr0); /* Enlarge drivability of LPDQS0-3, LPCLK */ 71 writel(0x30000000, &sbsc->sdwcr2); 72 73 writel(readl(&sbsc->sdpcr) | 0x80, &sbsc->sdpcr); 74 cmp_loop(&sbsc->sdpcr, 0x80, 0x80); 75 76 writel(0x00002710, &sbsc->sdgencnt); 77 cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); 78 79 writel(0x0000003f, &sbsc->sdmracr0); 80 writel(0x0, SDMRA1A); 81 writel(0x000001f4, &sbsc->sdgencnt); 82 cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); 83 84 writel(0x0000ff0a, &sbsc->sdmracr0); 85 if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE) 86 writel(0x0, SDMRA3A); 87 else 88 writel(0x0, SDMRA3B); 89 90 writel(0x00000032, &sbsc->sdgencnt); 91 cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); 92 93 if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE) { 94 writel(0x00002201, &sbsc->sdmracr0); 95 writel(0x0, SDMRA1A); 96 writel(0x00000402, &sbsc->sdmracr0); 97 writel(0x0, SDMRA1A); 98 writel(0x00000203, &sbsc->sdmracr0); /* MR3 register DS=2 */ 99 writel(0x0, SDMRA1A); 100 writel(0x0, SDMRA2A); 101 } else { 102 writel(0x00002201, &sbsc->sdmracr0); 103 writel(0x0, SDMRA1B); 104 writel(0x00000402, &sbsc->sdmracr0); 105 writel(0x0, SDMRA1B); 106 writel(0x00000203, &sbsc->sdmracr0); /* MR3 register DS=2 */ 107 writel(0x0, SDMRA1B); 108 writel(0x0, SDMRA2B); 109 } 110 111 writel(0x88800004, &sbsc->sdmrtmpcr); 112 writel(0x00000004, &sbsc->sdmrtmpmsk); 113 writel(0xa55a0032, &sbsc->rtcor); 114 writel(0xa55a000c, &sbsc->rtcorh); 115 writel(0xa55a2048, &sbsc->rtcsr); 116 writel(readl(&sbsc->sdcr0)|0x800, &sbsc->sdcr0); 117 writel(readl(&sbsc->sdcr1)|0x400, &sbsc->sdcr1); 118 writel(0xfff20000, &sbsc->zqccr); 119 120 /* SCBS2 only */ 121 if (sbsc == (struct sh73a0_sbsc *)SBSC2_BASE) { 122 writel(readl(&sbsc->sdpdcr0)|0x00030000, &sbsc->sdpdcr0); 123 writel(0xa5390000, &sbsc->dphycnt1); 124 writel(0x00001200, &sbsc->dphycnt0); 125 writel(0x07ce0000, &sbsc->dphycnt1); 126 writel(0x00001247, &sbsc->dphycnt0); 127 cmp_loop(&sbsc->dphycnt2, 0xffffffff, 0x07ce0000); 128 writel(readl(&sbsc->sdpdcr0) & 0xfffcffff, &sbsc->sdpdcr0); 129 } 130 } 131 132 void s_init(void) 133 { 134 struct sh73a0_rwdt *rwdt = (struct sh73a0_rwdt *)RWDT_BASE; 135 struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE; 136 struct sh73a0_sbsc_cpg_srcr *cpg_srcr = 137 (struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE; 138 struct sh73a0_sbsc *sbsc1 = (struct sh73a0_sbsc *)SBSC1_BASE; 139 struct sh73a0_sbsc *sbsc2 = (struct sh73a0_sbsc *)SBSC2_BASE; 140 struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE; 141 struct sh73a0_hpb_bscr *hpb_bscr = 142 (struct sh73a0_hpb_bscr *)HPBSCR_BASE; 143 144 /* Watchdog init */ 145 writew(0xA507, &rwdt->rwtcsra0); 146 147 /* Secure control register Init */ 148 #define LIFEC_SEC_SRC_BIT (1 << 15) 149 writel(readl(LIFEC_SEC_SRC) & ~LIFEC_SEC_SRC_BIT, LIFEC_SEC_SRC); 150 151 clrbits_le32(&cpg->smstpcr3, (1 << 15)); 152 clrbits_le32(&cpg_srcr->srcr3, (1 << 15)); 153 clrbits_le32(&cpg->smstpcr2, (1 << 18)); 154 clrbits_le32(&cpg_srcr->srcr2, (1 << 18)); 155 writel(0x0, &cpg->pllecr); 156 157 cmp_loop(&cpg->pllecr, 0x00000F00, 0x0); 158 cmp_loop(&cpg->frqcrb, 0x80000000, 0x0); 159 160 writel(0x2D000000, &cpg->pll0cr); 161 writel(0x17100000, &cpg->pll1cr); 162 writel(0x96235880, &cpg->frqcrb); 163 cmp_loop(&cpg->frqcrb, 0x80000000, 0x0); 164 165 writel(0xB, &cpg->flckcr); 166 clrbits_le32(&cpg->smstpcr0, (1 << 1)); 167 168 clrbits_le32(&cpg_srcr->srcr0, (1 << 1)); 169 writel(0x0514, &hpb_bscr->smgpiotime); 170 writel(0x0514, &hpb_bscr->smcmt2time); 171 writel(0x0514, &hpb_bscr->smcpgtime); 172 writel(0x0514, &hpb_bscr->smsysctime); 173 174 writel(0x00092000, &cpg->dvfscr4); 175 writel(0x000000DC, &cpg->dvfscr5); 176 writel(0x0, &cpg->pllecr); 177 cmp_loop(&cpg->pllecr, 0x00000F00, 0x0); 178 179 /* FRQCR Init */ 180 writel(0x0012453C, &cpg->frqcra); 181 writel(0x80431350, &cpg->frqcrb); /* ETM TRCLK 78MHz */ 182 cmp_loop(&cpg->frqcrb, 0x80000000, 0x0); 183 writel(0x00000B0B, &cpg->frqcrd); 184 cmp_loop(&cpg->frqcrd, 0x80000000, 0x0); 185 186 /* Clock Init */ 187 writel(0x00000003, PCLKCR); 188 writel(0x0000012F, &cpg->vclkcr1); 189 writel(0x00000119, &cpg->vclkcr2); 190 writel(0x00000119, &cpg->vclkcr3); 191 writel(0x00000002, &cpg->zbckcr); 192 writel(0x00000005, &cpg->flckcr); 193 writel(0x00000080, &cpg->sd0ckcr); 194 writel(0x00000080, &cpg->sd1ckcr); 195 writel(0x00000080, &cpg->sd2ckcr); 196 writel(0x0000003F, &cpg->fsiackcr); 197 writel(0x0000003F, &cpg->fsibckcr); 198 writel(0x00000080, &cpg->subckcr); 199 writel(0x0000000B, &cpg->spuackcr); 200 writel(0x0000000B, &cpg->spuvckcr); 201 writel(0x0000013F, &cpg->msuckcr); 202 writel(0x00000080, &cpg->hsickcr); 203 writel(0x0000003F, &cpg->mfck1cr); 204 writel(0x0000003F, &cpg->mfck2cr); 205 writel(0x00000107, &cpg->dsitckcr); 206 writel(0x00000313, &cpg->dsi0pckcr); 207 writel(0x0000130D, &cpg->dsi1pckcr); 208 writel(0x2A800E0E, &cpg->dsi0phycr); 209 writel(0x1E000000, &cpg->pll0cr); 210 writel(0x2D000000, &cpg->pll0cr); 211 writel(0x17100000, &cpg->pll1cr); 212 writel(0x27000080, &cpg->pll2cr); 213 writel(0x1D000000, &cpg->pll3cr); 214 writel(0x00080000, &cpg->pll0stpcr); 215 writel(0x000120C0, &cpg->pll1stpcr); 216 writel(0x00012000, &cpg->pll2stpcr); 217 writel(0x00000030, &cpg->pll3stpcr); 218 219 writel(0x0000000B, &cpg->pllecr); 220 cmp_loop(&cpg->pllecr, 0x00000B00, 0x00000B00); 221 222 writel(0x000120F0, &cpg->dvfscr3); 223 writel(0x00000020, &cpg->mpmode); 224 writel(0x0000028A, &cpg->vrefcr); 225 writel(0xE4628087, &cpg->rmstpcr0); 226 writel(0xFFFFFFFF, &cpg->rmstpcr1); 227 writel(0x53FFFFFF, &cpg->rmstpcr2); 228 writel(0xFFFFFFFF, &cpg->rmstpcr3); 229 writel(0x00800D3D, &cpg->rmstpcr4); 230 writel(0xFFFFF3FF, &cpg->rmstpcr5); 231 writel(0x00000000, &cpg->smstpcr2); 232 writel(0x00040000, &cpg_srcr->srcr2); 233 234 clrbits_le32(&cpg->pllecr, (1 << 3)); 235 cmp_loop(&cpg->pllecr, 0x00000800, 0x0); 236 237 writel(0x00000001, &hpb->hpbctrl6); 238 cmp_loop(&hpb->hpbctrl6, 0x1, 0x1); 239 240 writel(0x00001414, &cpg->frqcrd); 241 cmp_loop(&cpg->frqcrd, 0x80000000, 0x0); 242 243 writel(0x1d000000, &cpg->pll3cr); 244 setbits_le32(&cpg->pllecr, (1 << 3)); 245 cmp_loop(&cpg->pllecr, 0x800, 0x800); 246 247 /* SBSC1 Init*/ 248 sbsc_init(sbsc1); 249 250 /* SBSC2 Init*/ 251 sbsc_init(sbsc2); 252 253 writel(0x00000b0b, &cpg->frqcrd); 254 cmp_loop(&cpg->frqcrd, 0x80000000, 0x0); 255 writel(0xfffffffc, &cpg->cpgxxcs4); 256 } 257 258 int board_early_init_f(void) 259 { 260 struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE; 261 struct sh73a0_bsc *bsc = (struct sh73a0_bsc *)BSC_BASE; 262 struct sh73a0_sbsc_cpg_srcr *cpg_srcr = 263 (struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE; 264 265 writel(CS0BCR_D, &bsc->cs0bcr); 266 writel(CS4BCR_D, &bsc->cs4bcr); 267 writel(CS0WCR_D, &bsc->cs0wcr); 268 writel(CS4WCR_D, &bsc->cs4wcr); 269 270 clrsetbits_le32(&bsc->cmncr, ~CMNCR_BROMMD, CMNCR_BROMMD); 271 272 clrbits_le32(&cpg->smstpcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); 273 clrbits_le32(&cpg_srcr->srcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); 274 clrbits_le32(&cpg->smstpcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1)); 275 clrbits_le32(&cpg_srcr->srcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1)); 276 writel(VCLKCR1_D, &cpg->vclkcr1); 277 278 /* Setup SCIF4 / workaround */ 279 writeb(0x12, PORT32CR); 280 writeb(0x22, PORT33CR); 281 writeb(0x12, PORT34CR); 282 writeb(0x22, PORT35CR); 283 284 return 0; 285 } 286 287 void adjust_core_voltage(void) 288 { 289 u8 data; 290 291 data = 0x35; 292 i2c_set_bus_num(0); 293 i2c_write(0x40, 3, 1, &data, 1); 294 } 295 296 int board_init(void) 297 { 298 adjust_core_voltage(); 299 sh73a0_pinmux_init(); 300 301 /* SCIFA 4 */ 302 gpio_request(GPIO_FN_SCIFA4_TXD, NULL); 303 gpio_request(GPIO_FN_SCIFA4_RXD, NULL); 304 gpio_request(GPIO_FN_SCIFA4_RTS_, NULL); 305 gpio_request(GPIO_FN_SCIFA4_CTS_, NULL); 306 307 /* Ethernet/SMSC */ 308 gpio_request(GPIO_PORT224, NULL); 309 gpio_direction_input(GPIO_PORT224); 310 311 /* SMSC/USB */ 312 gpio_request(GPIO_FN_CS4_, NULL); 313 314 /* MMCIF */ 315 gpio_request(GPIO_FN_MMCCLK0, NULL); 316 gpio_request(GPIO_FN_MMCCMD0_PU, NULL); 317 gpio_request(GPIO_FN_MMCD0_0_PU, NULL); 318 gpio_request(GPIO_FN_MMCD0_1_PU, NULL); 319 gpio_request(GPIO_FN_MMCD0_2_PU, NULL); 320 gpio_request(GPIO_FN_MMCD0_3_PU, NULL); 321 gpio_request(GPIO_FN_MMCD0_4_PU, NULL); 322 gpio_request(GPIO_FN_MMCD0_5_PU, NULL); 323 gpio_request(GPIO_FN_MMCD0_6_PU, NULL); 324 gpio_request(GPIO_FN_MMCD0_7_PU, NULL); 325 326 /* SDHI */ 327 gpio_request(GPIO_FN_SDHIWP0, NULL); 328 gpio_request(GPIO_FN_SDHICD0, NULL); 329 gpio_request(GPIO_FN_SDHICMD0, NULL); 330 gpio_request(GPIO_FN_SDHICLK0, NULL); 331 gpio_request(GPIO_FN_SDHID0_3, NULL); 332 gpio_request(GPIO_FN_SDHID0_2, NULL); 333 gpio_request(GPIO_FN_SDHID0_1, NULL); 334 gpio_request(GPIO_FN_SDHID0_0, NULL); 335 gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL); 336 gpio_request(GPIO_PORT15, NULL); 337 gpio_direction_output(GPIO_PORT15, 1); 338 339 /* I2C */ 340 gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL); 341 gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL); 342 gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL); 343 gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL); 344 345 gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); 346 347 return 0; 348 } 349 350 int dram_init(void) 351 { 352 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 353 return 0; 354 } 355 356 int board_eth_init(bd_t *bis) 357 { 358 int ret = 0; 359 #ifdef CONFIG_SMC911X 360 ret = smc911x_initialize(0, CONFIG_SMC911X_BASE); 361 #endif 362 return ret; 363 } 364 365 void reset_cpu(ulong addr) 366 { 367 /* Soft Power On Reset */ 368 writel((1 << 31), RESCNT2); 369 } 370