1 /* 2 * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 3 * (C) Copyright 2012 Renesas Solutions Corp. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <asm/io.h> 26 #include <asm/arch/sys_proto.h> 27 #include <asm/gpio.h> 28 #include <netdev.h> 29 #include <i2c.h> 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 #define CS0BCR_D (0x06C00400) 34 #define CS4BCR_D (0x16c90400) 35 #define CS0WCR_D (0x55062C42) 36 #define CS4WCR_D (0x1e071dc3) 37 38 #define CMNCR_BROMMD0 (1 << 21) 39 #define CMNCR_BROMMD1 (1 << 22) 40 #define CMNCR_BROMMD (CMNCR_BROMMD0|CMNCR_BROMMD1) 41 #define VCLKCR1_D (0x27) 42 43 #define SMSTPCR1_CMT0 (1 << 24) 44 #define SMSTPCR1_I2C0 (1 << 16) 45 #define SMSTPCR3_USB (1 << 22) 46 47 #define PORT32CR (0xE6051020) 48 #define PORT33CR (0xE6051021) 49 #define PORT34CR (0xE6051022) 50 #define PORT35CR (0xE6051023) 51 52 static int cmp_loop(u32 *addr, u32 data, u32 cmp) 53 { 54 int err = -1; 55 int timeout = 100; 56 u32 value; 57 58 while (timeout > 0) { 59 value = readl(addr); 60 if ((value & data) == cmp) { 61 err = 0; 62 break; 63 } 64 timeout--; 65 } 66 67 return err; 68 } 69 70 /* SBSC Init function */ 71 static void sbsc_init(struct sh73a0_sbsc *sbsc) 72 { 73 writel(readl(&sbsc->dllcnt0)|0x2, &sbsc->dllcnt0); 74 writel(0x5, &sbsc->sdgencnt); 75 cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); 76 77 writel(0xacc90159, &sbsc->sdcr0); 78 writel(0x00010059, &sbsc->sdcr1); 79 writel(0x50874114, &sbsc->sdwcrc0); 80 writel(0x33199b37, &sbsc->sdwcrc1); 81 writel(0x008f2313, &sbsc->sdwcrc2); 82 writel(0x31020707, &sbsc->sdwcr00); 83 writel(0x0017040a, &sbsc->sdwcr01); 84 writel(0x31020707, &sbsc->sdwcr10); 85 writel(0x0017040a, &sbsc->sdwcr11); 86 writel(0x05555555, &sbsc->sddrvcr0); 87 writel(0x30000000, &sbsc->sdwcr2); 88 89 writel(readl(&sbsc->sdpcr) | 0x80, &sbsc->sdpcr); 90 cmp_loop(&sbsc->sdpcr, 0x80, 0x80); 91 92 writel(0x00002710, &sbsc->sdgencnt); 93 cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); 94 95 writel(0x0000003f, &sbsc->sdmracr0); 96 writel(0x0, SDMRA1A); 97 writel(0x000001f4, &sbsc->sdgencnt); 98 cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); 99 100 writel(0x0000ff0a, &sbsc->sdmracr0); 101 if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE) 102 writel(0x0, SDMRA3A); 103 else 104 writel(0x0, SDMRA3B); 105 106 writel(0x00000032, &sbsc->sdgencnt); 107 cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); 108 109 if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE) { 110 writel(0x00002201, &sbsc->sdmracr0); 111 writel(0x0, SDMRA1A); 112 writel(0x00000402, &sbsc->sdmracr0); 113 writel(0x0, SDMRA1A); 114 writel(0x00000403, &sbsc->sdmracr0); 115 writel(0x0, SDMRA1A); 116 writel(0x0, SDMRA2A); 117 } else { 118 writel(0x00002201, &sbsc->sdmracr0); 119 writel(0x0, SDMRA1B); 120 writel(0x00000402, &sbsc->sdmracr0); 121 writel(0x0, SDMRA1B); 122 writel(0x00000403, &sbsc->sdmracr0); 123 writel(0x0, SDMRA1B); 124 writel(0x0, SDMRA2B); 125 } 126 127 writel(0x88800004, &sbsc->sdmrtmpcr); 128 writel(0x00000004, &sbsc->sdmrtmpmsk); 129 writel(0xa55a0032, &sbsc->rtcor); 130 writel(0xa55a000c, &sbsc->rtcorh); 131 writel(0xa55a2048, &sbsc->rtcsr); 132 writel(readl(&sbsc->sdcr0)|0x800, &sbsc->sdcr0); 133 writel(readl(&sbsc->sdcr1)|0x400, &sbsc->sdcr1); 134 writel(0xfff20000, &sbsc->zqccr); 135 136 /* SCBS2 only */ 137 if (sbsc == (struct sh73a0_sbsc *)SBSC2_BASE) { 138 writel(readl(&sbsc->sdpdcr0)|0x00030000, &sbsc->sdpdcr0); 139 writel(0xa5390000, &sbsc->dphycnt1); 140 writel(0x00001200, &sbsc->dphycnt0); 141 writel(0x07ce0000, &sbsc->dphycnt1); 142 writel(0x00001247, &sbsc->dphycnt0); 143 cmp_loop(&sbsc->dphycnt2, 0xffffffff, 0x07ce0000); 144 writel(readl(&sbsc->sdpdcr0) & 0xfffcffff, &sbsc->sdpdcr0); 145 } 146 } 147 148 void s_init(void) 149 { 150 struct sh73a0_rwdt *rwdt = (struct sh73a0_rwdt *)RWDT_BASE; 151 struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE; 152 struct sh73a0_sbsc_cpg_srcr *cpg_srcr = 153 (struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE; 154 struct sh73a0_sbsc *sbsc1 = (struct sh73a0_sbsc *)SBSC1_BASE; 155 struct sh73a0_sbsc *sbsc2 = (struct sh73a0_sbsc *)SBSC2_BASE; 156 struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE; 157 struct sh73a0_hpb_bscr *hpb_bscr = 158 (struct sh73a0_hpb_bscr *)HPBSCR_BASE; 159 160 /* Watchdog init */ 161 writew(0xA507, &rwdt->rwtcsra0); 162 163 /* Secure control register Init */ 164 #define LIFEC_SEC_SRC_BIT (1 << 15) 165 writel(readl(LIFEC_SEC_SRC) & ~LIFEC_SEC_SRC_BIT, LIFEC_SEC_SRC); 166 167 clrbits_le32(&cpg->smstpcr3, (1 << 15)); 168 clrbits_le32(&cpg_srcr->srcr3, (1 << 15)); 169 clrbits_le32(&cpg->smstpcr2, (1 << 18)); 170 clrbits_le32(&cpg_srcr->srcr2, (1 << 18)); 171 writel(0x0, &cpg->pllecr); 172 173 cmp_loop(&cpg->pllecr, 0x00000F00, 0x0); 174 cmp_loop(&cpg->frqcrb, 0x80000000, 0x0); 175 176 writel(0x2D000000, &cpg->pll0cr); 177 writel(0x17100000, &cpg->pll1cr); 178 writel(0x96235880, &cpg->frqcrb); 179 cmp_loop(&cpg->frqcrb, 0x80000000, 0x0); 180 181 writel(0xB, &cpg->flckcr); 182 clrbits_le32(&cpg->smstpcr0, (1 << 1)); 183 184 clrbits_le32(&cpg_srcr->srcr0, (1 << 1)); 185 writel(0x0514, &hpb_bscr->smgpiotime); 186 writel(0x0514, &hpb_bscr->smcmt2time); 187 writel(0x0514, &hpb_bscr->smcpgtime); 188 writel(0x0514, &hpb_bscr->smsysctime); 189 190 writel(0x00092000, &cpg->dvfscr4); 191 writel(0x000000DC, &cpg->dvfscr5); 192 writel(0x0, &cpg->pllecr); 193 cmp_loop(&cpg->pllecr, 0x00000F00, 0x0); 194 195 /* FRQCR Init */ 196 writel(0x0012453C, &cpg->frqcra); 197 writel(0x80331350, &cpg->frqcrb); 198 cmp_loop(&cpg->frqcrb, 0x80000000, 0x0); 199 writel(0x00000B0B, &cpg->frqcrd); 200 cmp_loop(&cpg->frqcrd, 0x80000000, 0x0); 201 202 /* Clock Init */ 203 writel(0x00000003, PCLKCR); 204 writel(0x0000012F, &cpg->vclkcr1); 205 writel(0x00000119, &cpg->vclkcr2); 206 writel(0x00000119, &cpg->vclkcr3); 207 writel(0x00000002, &cpg->zbckcr); 208 writel(0x00000005, &cpg->flckcr); 209 writel(0x00000080, &cpg->sd0ckcr); 210 writel(0x00000080, &cpg->sd1ckcr); 211 writel(0x00000080, &cpg->sd2ckcr); 212 writel(0x0000003F, &cpg->fsiackcr); 213 writel(0x0000003F, &cpg->fsibckcr); 214 writel(0x00000080, &cpg->subckcr); 215 writel(0x0000000B, &cpg->spuackcr); 216 writel(0x0000000B, &cpg->spuvckcr); 217 writel(0x0000013F, &cpg->msuckcr); 218 writel(0x00000080, &cpg->hsickcr); 219 writel(0x0000003F, &cpg->mfck1cr); 220 writel(0x0000003F, &cpg->mfck2cr); 221 writel(0x00000107, &cpg->dsitckcr); 222 writel(0x00000313, &cpg->dsi0pckcr); 223 writel(0x0000130D, &cpg->dsi1pckcr); 224 writel(0x2A800E0E, &cpg->dsi0phycr); 225 writel(0x1E000000, &cpg->pll0cr); 226 writel(0x2D000000, &cpg->pll0cr); 227 writel(0x17100000, &cpg->pll1cr); 228 writel(0x27000080, &cpg->pll2cr); 229 writel(0x1D000000, &cpg->pll3cr); 230 writel(0x00080000, &cpg->pll0stpcr); 231 writel(0x000120C0, &cpg->pll1stpcr); 232 writel(0x00012000, &cpg->pll2stpcr); 233 writel(0x00000030, &cpg->pll3stpcr); 234 235 writel(0x0000000B, &cpg->pllecr); 236 cmp_loop(&cpg->pllecr, 0x00000B00, 0x00000B00); 237 238 writel(0x000120F0, &cpg->dvfscr3); 239 writel(0x00000020, &cpg->mpmode); 240 writel(0x0000028A, &cpg->vrefcr); 241 writel(0xE4628087, &cpg->rmstpcr0); 242 writel(0xFFFFFFFF, &cpg->rmstpcr1); 243 writel(0x53FFFFFF, &cpg->rmstpcr2); 244 writel(0xFFFFFFFF, &cpg->rmstpcr3); 245 writel(0x00800D3D, &cpg->rmstpcr4); 246 writel(0xFFFFF3FF, &cpg->rmstpcr5); 247 writel(0x00000000, &cpg->smstpcr2); 248 writel(0x00040000, &cpg_srcr->srcr2); 249 250 clrbits_le32(&cpg->pllecr, (1 << 3)); 251 cmp_loop(&cpg->pllecr, 0x00000800, 0x0); 252 253 writel(0x00000001, &hpb->hpbctrl6); 254 cmp_loop(&hpb->hpbctrl6, 0x1, 0x1); 255 256 writel(0x00001414, &cpg->frqcrd); 257 cmp_loop(&cpg->frqcrd, 0x80000000, 0x0); 258 259 writel(0x1d000000, &cpg->pll3cr); 260 setbits_le32(&cpg->pllecr, (1 << 3)); 261 cmp_loop(&cpg->pllecr, 0x800, 0x800); 262 263 /* SBSC1 Init*/ 264 sbsc_init(sbsc1); 265 266 /* SBSC2 Init*/ 267 sbsc_init(sbsc2); 268 269 writel(0x00000b0b, &cpg->frqcrd); 270 cmp_loop(&cpg->frqcrd, 0x80000000, 0x0); 271 writel(0xfffffffc, &cpg->cpgxxcs4); 272 } 273 274 int board_early_init_f(void) 275 { 276 struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE; 277 struct sh73a0_bsc *bsc = (struct sh73a0_bsc *)BSC_BASE; 278 struct sh73a0_sbsc_cpg_srcr *cpg_srcr = 279 (struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE; 280 281 writel(CS0BCR_D, &bsc->cs0bcr); 282 writel(CS4BCR_D, &bsc->cs4bcr); 283 writel(CS0WCR_D, &bsc->cs0wcr); 284 writel(CS4WCR_D, &bsc->cs4wcr); 285 286 clrsetbits_le32(&bsc->cmncr, ~CMNCR_BROMMD, CMNCR_BROMMD); 287 288 clrbits_le32(&cpg->smstpcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); 289 clrbits_le32(&cpg_srcr->srcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); 290 clrbits_le32(&cpg->smstpcr3, SMSTPCR3_USB); 291 clrbits_le32(&cpg_srcr->srcr3, SMSTPCR3_USB); 292 writel(VCLKCR1_D, &cpg->vclkcr1); 293 294 /* Setup SCIF4 / workaround */ 295 writeb(0x12, PORT32CR); 296 writeb(0x22, PORT33CR); 297 writeb(0x12, PORT34CR); 298 writeb(0x22, PORT35CR); 299 300 return 0; 301 } 302 303 int board_init(void) 304 { 305 sh73a0_pinmux_init(); 306 307 /* SCIFA 4 */ 308 gpio_request(GPIO_FN_SCIFA4_TXD, NULL); 309 gpio_request(GPIO_FN_SCIFA4_RXD, NULL); 310 gpio_request(GPIO_FN_SCIFA4_RTS_, NULL); 311 gpio_request(GPIO_FN_SCIFA4_CTS_, NULL); 312 313 /* Ethernet/SMSC */ 314 gpio_request(GPIO_PORT224, NULL); 315 gpio_direction_input(GPIO_PORT224); 316 317 /* SMSC/USB */ 318 gpio_request(GPIO_FN_CS4_, NULL); 319 320 /* MMCIF */ 321 gpio_request(GPIO_FN_MMCCLK0, NULL); 322 gpio_request(GPIO_FN_MMCCMD0_PU, NULL); 323 gpio_request(GPIO_FN_MMCD0_0_PU, NULL); 324 gpio_request(GPIO_FN_MMCD0_1_PU, NULL); 325 gpio_request(GPIO_FN_MMCD0_2_PU, NULL); 326 gpio_request(GPIO_FN_MMCD0_3_PU, NULL); 327 gpio_request(GPIO_FN_MMCD0_4_PU, NULL); 328 gpio_request(GPIO_FN_MMCD0_5_PU, NULL); 329 gpio_request(GPIO_FN_MMCD0_6_PU, NULL); 330 gpio_request(GPIO_FN_MMCD0_7_PU, NULL); 331 332 /* SDHI */ 333 gpio_request(GPIO_FN_SDHIWP0, NULL); 334 gpio_request(GPIO_FN_SDHICD0, NULL); 335 gpio_request(GPIO_FN_SDHICMD0, NULL); 336 gpio_request(GPIO_FN_SDHICLK0, NULL); 337 gpio_request(GPIO_FN_SDHID0_3, NULL); 338 gpio_request(GPIO_FN_SDHID0_2, NULL); 339 gpio_request(GPIO_FN_SDHID0_1, NULL); 340 gpio_request(GPIO_FN_SDHID0_0, NULL); 341 gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL); 342 gpio_request(GPIO_PORT15, NULL); 343 gpio_direction_output(GPIO_PORT15, 1); 344 345 /* I2C */ 346 gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL); 347 gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL); 348 349 gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); 350 351 return 0; 352 } 353 354 const struct rmobile_sysinfo sysinfo = { 355 CONFIG_RMOBILE_BOARD_STRING 356 }; 357 358 int dram_init(void) 359 { 360 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 361 return 0; 362 } 363 364 int board_eth_init(bd_t *bis) 365 { 366 int ret = 0; 367 #ifdef CONFIG_SMC911X 368 ret = smc911x_initialize(0, CONFIG_SMC911X_BASE); 369 #endif 370 return ret; 371 } 372 373 void reset_cpu(ulong addr) 374 { 375 /* Soft Power On Reset */ 376 writel((1 << 31), RESCNT2); 377 } 378