1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 28d811ca3SNobuhiro Iwamatsu /* 38d811ca3SNobuhiro Iwamatsu * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 48d811ca3SNobuhiro Iwamatsu * (C) Copyright 2012 Renesas Solutions Corp. 58d811ca3SNobuhiro Iwamatsu */ 68d811ca3SNobuhiro Iwamatsu 78d811ca3SNobuhiro Iwamatsu #include <common.h> 88d811ca3SNobuhiro Iwamatsu #include <asm/io.h> 98d811ca3SNobuhiro Iwamatsu #include <asm/arch/sys_proto.h> 108d811ca3SNobuhiro Iwamatsu #include <asm/gpio.h> 118d811ca3SNobuhiro Iwamatsu #include <netdev.h> 128d811ca3SNobuhiro Iwamatsu #include <i2c.h> 138d811ca3SNobuhiro Iwamatsu 148d811ca3SNobuhiro Iwamatsu DECLARE_GLOBAL_DATA_PTR; 158d811ca3SNobuhiro Iwamatsu 168d811ca3SNobuhiro Iwamatsu #define CS0BCR_D (0x06C00400) 17d95a96a0STetsuyuki Kobayashi #define CS4BCR_D (0x16c90400) 188d811ca3SNobuhiro Iwamatsu #define CS0WCR_D (0x55062C42) 19d95a96a0STetsuyuki Kobayashi #define CS4WCR_D (0x1e071dc3) 20d95a96a0STetsuyuki Kobayashi 218d811ca3SNobuhiro Iwamatsu #define CMNCR_BROMMD0 (1 << 21) 228d811ca3SNobuhiro Iwamatsu #define CMNCR_BROMMD1 (1 << 22) 238d811ca3SNobuhiro Iwamatsu #define CMNCR_BROMMD (CMNCR_BROMMD0|CMNCR_BROMMD1) 248d811ca3SNobuhiro Iwamatsu #define VCLKCR1_D (0x27) 258d811ca3SNobuhiro Iwamatsu 268d811ca3SNobuhiro Iwamatsu #define SMSTPCR1_CMT0 (1 << 24) 278d811ca3SNobuhiro Iwamatsu #define SMSTPCR1_I2C0 (1 << 16) 288d811ca3SNobuhiro Iwamatsu #define SMSTPCR3_USB (1 << 22) 29937b6862STetsuyuki Kobayashi #define SMSTPCR3_I2C1 (1 << 23) 308d811ca3SNobuhiro Iwamatsu 318d811ca3SNobuhiro Iwamatsu #define PORT32CR (0xE6051020) 328d811ca3SNobuhiro Iwamatsu #define PORT33CR (0xE6051021) 338d811ca3SNobuhiro Iwamatsu #define PORT34CR (0xE6051022) 348d811ca3SNobuhiro Iwamatsu #define PORT35CR (0xE6051023) 358d811ca3SNobuhiro Iwamatsu 368d811ca3SNobuhiro Iwamatsu static int cmp_loop(u32 *addr, u32 data, u32 cmp) 378d811ca3SNobuhiro Iwamatsu { 388d811ca3SNobuhiro Iwamatsu int err = -1; 398d811ca3SNobuhiro Iwamatsu int timeout = 100; 408d811ca3SNobuhiro Iwamatsu u32 value; 418d811ca3SNobuhiro Iwamatsu 428d811ca3SNobuhiro Iwamatsu while (timeout > 0) { 438d811ca3SNobuhiro Iwamatsu value = readl(addr); 448d811ca3SNobuhiro Iwamatsu if ((value & data) == cmp) { 458d811ca3SNobuhiro Iwamatsu err = 0; 468d811ca3SNobuhiro Iwamatsu break; 478d811ca3SNobuhiro Iwamatsu } 488d811ca3SNobuhiro Iwamatsu timeout--; 498d811ca3SNobuhiro Iwamatsu } 508d811ca3SNobuhiro Iwamatsu 518d811ca3SNobuhiro Iwamatsu return err; 528d811ca3SNobuhiro Iwamatsu } 538d811ca3SNobuhiro Iwamatsu 548d811ca3SNobuhiro Iwamatsu /* SBSC Init function */ 558d811ca3SNobuhiro Iwamatsu static void sbsc_init(struct sh73a0_sbsc *sbsc) 568d811ca3SNobuhiro Iwamatsu { 578d811ca3SNobuhiro Iwamatsu writel(readl(&sbsc->dllcnt0)|0x2, &sbsc->dllcnt0); 588d811ca3SNobuhiro Iwamatsu writel(0x5, &sbsc->sdgencnt); 598d811ca3SNobuhiro Iwamatsu cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); 608d811ca3SNobuhiro Iwamatsu 618d811ca3SNobuhiro Iwamatsu writel(0xacc90159, &sbsc->sdcr0); 628d811ca3SNobuhiro Iwamatsu writel(0x00010059, &sbsc->sdcr1); 638d811ca3SNobuhiro Iwamatsu writel(0x50874114, &sbsc->sdwcrc0); 648d811ca3SNobuhiro Iwamatsu writel(0x33199b37, &sbsc->sdwcrc1); 658d811ca3SNobuhiro Iwamatsu writel(0x008f2313, &sbsc->sdwcrc2); 668d811ca3SNobuhiro Iwamatsu writel(0x31020707, &sbsc->sdwcr00); 678d811ca3SNobuhiro Iwamatsu writel(0x0017040a, &sbsc->sdwcr01); 688d811ca3SNobuhiro Iwamatsu writel(0x31020707, &sbsc->sdwcr10); 698d811ca3SNobuhiro Iwamatsu writel(0x0017040a, &sbsc->sdwcr11); 70f68847faSTetsuyuki Kobayashi writel(0x055557ff, &sbsc->sddrvcr0); /* Enlarge drivability of LPDQS0-3, LPCLK */ 718d811ca3SNobuhiro Iwamatsu writel(0x30000000, &sbsc->sdwcr2); 728d811ca3SNobuhiro Iwamatsu 738d811ca3SNobuhiro Iwamatsu writel(readl(&sbsc->sdpcr) | 0x80, &sbsc->sdpcr); 748d811ca3SNobuhiro Iwamatsu cmp_loop(&sbsc->sdpcr, 0x80, 0x80); 758d811ca3SNobuhiro Iwamatsu 768d811ca3SNobuhiro Iwamatsu writel(0x00002710, &sbsc->sdgencnt); 778d811ca3SNobuhiro Iwamatsu cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); 788d811ca3SNobuhiro Iwamatsu 798d811ca3SNobuhiro Iwamatsu writel(0x0000003f, &sbsc->sdmracr0); 808d811ca3SNobuhiro Iwamatsu writel(0x0, SDMRA1A); 818d811ca3SNobuhiro Iwamatsu writel(0x000001f4, &sbsc->sdgencnt); 828d811ca3SNobuhiro Iwamatsu cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); 838d811ca3SNobuhiro Iwamatsu 848d811ca3SNobuhiro Iwamatsu writel(0x0000ff0a, &sbsc->sdmracr0); 858d811ca3SNobuhiro Iwamatsu if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE) 868d811ca3SNobuhiro Iwamatsu writel(0x0, SDMRA3A); 878d811ca3SNobuhiro Iwamatsu else 888d811ca3SNobuhiro Iwamatsu writel(0x0, SDMRA3B); 898d811ca3SNobuhiro Iwamatsu 908d811ca3SNobuhiro Iwamatsu writel(0x00000032, &sbsc->sdgencnt); 918d811ca3SNobuhiro Iwamatsu cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); 928d811ca3SNobuhiro Iwamatsu 938d811ca3SNobuhiro Iwamatsu if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE) { 948d811ca3SNobuhiro Iwamatsu writel(0x00002201, &sbsc->sdmracr0); 958d811ca3SNobuhiro Iwamatsu writel(0x0, SDMRA1A); 968d811ca3SNobuhiro Iwamatsu writel(0x00000402, &sbsc->sdmracr0); 978d811ca3SNobuhiro Iwamatsu writel(0x0, SDMRA1A); 98f68847faSTetsuyuki Kobayashi writel(0x00000203, &sbsc->sdmracr0); /* MR3 register DS=2 */ 998d811ca3SNobuhiro Iwamatsu writel(0x0, SDMRA1A); 1008d811ca3SNobuhiro Iwamatsu writel(0x0, SDMRA2A); 1018d811ca3SNobuhiro Iwamatsu } else { 1028d811ca3SNobuhiro Iwamatsu writel(0x00002201, &sbsc->sdmracr0); 1038d811ca3SNobuhiro Iwamatsu writel(0x0, SDMRA1B); 1048d811ca3SNobuhiro Iwamatsu writel(0x00000402, &sbsc->sdmracr0); 1058d811ca3SNobuhiro Iwamatsu writel(0x0, SDMRA1B); 106f68847faSTetsuyuki Kobayashi writel(0x00000203, &sbsc->sdmracr0); /* MR3 register DS=2 */ 1078d811ca3SNobuhiro Iwamatsu writel(0x0, SDMRA1B); 1088d811ca3SNobuhiro Iwamatsu writel(0x0, SDMRA2B); 1098d811ca3SNobuhiro Iwamatsu } 1108d811ca3SNobuhiro Iwamatsu 1118d811ca3SNobuhiro Iwamatsu writel(0x88800004, &sbsc->sdmrtmpcr); 1128d811ca3SNobuhiro Iwamatsu writel(0x00000004, &sbsc->sdmrtmpmsk); 1138d811ca3SNobuhiro Iwamatsu writel(0xa55a0032, &sbsc->rtcor); 1148d811ca3SNobuhiro Iwamatsu writel(0xa55a000c, &sbsc->rtcorh); 1158d811ca3SNobuhiro Iwamatsu writel(0xa55a2048, &sbsc->rtcsr); 1168d811ca3SNobuhiro Iwamatsu writel(readl(&sbsc->sdcr0)|0x800, &sbsc->sdcr0); 1178d811ca3SNobuhiro Iwamatsu writel(readl(&sbsc->sdcr1)|0x400, &sbsc->sdcr1); 1188d811ca3SNobuhiro Iwamatsu writel(0xfff20000, &sbsc->zqccr); 1198d811ca3SNobuhiro Iwamatsu 1208d811ca3SNobuhiro Iwamatsu /* SCBS2 only */ 1218d811ca3SNobuhiro Iwamatsu if (sbsc == (struct sh73a0_sbsc *)SBSC2_BASE) { 1228d811ca3SNobuhiro Iwamatsu writel(readl(&sbsc->sdpdcr0)|0x00030000, &sbsc->sdpdcr0); 1238d811ca3SNobuhiro Iwamatsu writel(0xa5390000, &sbsc->dphycnt1); 1248d811ca3SNobuhiro Iwamatsu writel(0x00001200, &sbsc->dphycnt0); 1258d811ca3SNobuhiro Iwamatsu writel(0x07ce0000, &sbsc->dphycnt1); 1268d811ca3SNobuhiro Iwamatsu writel(0x00001247, &sbsc->dphycnt0); 1278d811ca3SNobuhiro Iwamatsu cmp_loop(&sbsc->dphycnt2, 0xffffffff, 0x07ce0000); 1288d811ca3SNobuhiro Iwamatsu writel(readl(&sbsc->sdpdcr0) & 0xfffcffff, &sbsc->sdpdcr0); 1298d811ca3SNobuhiro Iwamatsu } 1308d811ca3SNobuhiro Iwamatsu } 1318d811ca3SNobuhiro Iwamatsu 1328d811ca3SNobuhiro Iwamatsu void s_init(void) 1338d811ca3SNobuhiro Iwamatsu { 1348d811ca3SNobuhiro Iwamatsu struct sh73a0_rwdt *rwdt = (struct sh73a0_rwdt *)RWDT_BASE; 1358d811ca3SNobuhiro Iwamatsu struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE; 1368d811ca3SNobuhiro Iwamatsu struct sh73a0_sbsc_cpg_srcr *cpg_srcr = 1378d811ca3SNobuhiro Iwamatsu (struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE; 1388d811ca3SNobuhiro Iwamatsu struct sh73a0_sbsc *sbsc1 = (struct sh73a0_sbsc *)SBSC1_BASE; 1398d811ca3SNobuhiro Iwamatsu struct sh73a0_sbsc *sbsc2 = (struct sh73a0_sbsc *)SBSC2_BASE; 1408d811ca3SNobuhiro Iwamatsu struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE; 1418d811ca3SNobuhiro Iwamatsu struct sh73a0_hpb_bscr *hpb_bscr = 1428d811ca3SNobuhiro Iwamatsu (struct sh73a0_hpb_bscr *)HPBSCR_BASE; 1438d811ca3SNobuhiro Iwamatsu 1448d811ca3SNobuhiro Iwamatsu /* Watchdog init */ 1458d811ca3SNobuhiro Iwamatsu writew(0xA507, &rwdt->rwtcsra0); 1468d811ca3SNobuhiro Iwamatsu 1478d811ca3SNobuhiro Iwamatsu /* Secure control register Init */ 1488d811ca3SNobuhiro Iwamatsu #define LIFEC_SEC_SRC_BIT (1 << 15) 1498d811ca3SNobuhiro Iwamatsu writel(readl(LIFEC_SEC_SRC) & ~LIFEC_SEC_SRC_BIT, LIFEC_SEC_SRC); 1508d811ca3SNobuhiro Iwamatsu 151a1263312STetsuyuki Kobayashi clrbits_le32(&cpg->smstpcr3, (1 << 15)); 1528d811ca3SNobuhiro Iwamatsu clrbits_le32(&cpg_srcr->srcr3, (1 << 15)); 1538d811ca3SNobuhiro Iwamatsu clrbits_le32(&cpg->smstpcr2, (1 << 18)); 1548d811ca3SNobuhiro Iwamatsu clrbits_le32(&cpg_srcr->srcr2, (1 << 18)); 1558d811ca3SNobuhiro Iwamatsu writel(0x0, &cpg->pllecr); 1568d811ca3SNobuhiro Iwamatsu 1578d811ca3SNobuhiro Iwamatsu cmp_loop(&cpg->pllecr, 0x00000F00, 0x0); 1588d811ca3SNobuhiro Iwamatsu cmp_loop(&cpg->frqcrb, 0x80000000, 0x0); 1598d811ca3SNobuhiro Iwamatsu 1608d811ca3SNobuhiro Iwamatsu writel(0x2D000000, &cpg->pll0cr); 1618d811ca3SNobuhiro Iwamatsu writel(0x17100000, &cpg->pll1cr); 1628d811ca3SNobuhiro Iwamatsu writel(0x96235880, &cpg->frqcrb); 1638d811ca3SNobuhiro Iwamatsu cmp_loop(&cpg->frqcrb, 0x80000000, 0x0); 1648d811ca3SNobuhiro Iwamatsu 1658d811ca3SNobuhiro Iwamatsu writel(0xB, &cpg->flckcr); 1668d811ca3SNobuhiro Iwamatsu clrbits_le32(&cpg->smstpcr0, (1 << 1)); 1678d811ca3SNobuhiro Iwamatsu 1688d811ca3SNobuhiro Iwamatsu clrbits_le32(&cpg_srcr->srcr0, (1 << 1)); 1698d811ca3SNobuhiro Iwamatsu writel(0x0514, &hpb_bscr->smgpiotime); 1708d811ca3SNobuhiro Iwamatsu writel(0x0514, &hpb_bscr->smcmt2time); 1718d811ca3SNobuhiro Iwamatsu writel(0x0514, &hpb_bscr->smcpgtime); 1728d811ca3SNobuhiro Iwamatsu writel(0x0514, &hpb_bscr->smsysctime); 1738d811ca3SNobuhiro Iwamatsu 1748d811ca3SNobuhiro Iwamatsu writel(0x00092000, &cpg->dvfscr4); 1758d811ca3SNobuhiro Iwamatsu writel(0x000000DC, &cpg->dvfscr5); 1768d811ca3SNobuhiro Iwamatsu writel(0x0, &cpg->pllecr); 1778d811ca3SNobuhiro Iwamatsu cmp_loop(&cpg->pllecr, 0x00000F00, 0x0); 1788d811ca3SNobuhiro Iwamatsu 1798d811ca3SNobuhiro Iwamatsu /* FRQCR Init */ 1808d811ca3SNobuhiro Iwamatsu writel(0x0012453C, &cpg->frqcra); 181b0404ea1STetsuyuki Kobayashi writel(0x80431350, &cpg->frqcrb); /* ETM TRCLK 78MHz */ 1828d811ca3SNobuhiro Iwamatsu cmp_loop(&cpg->frqcrb, 0x80000000, 0x0); 1838d811ca3SNobuhiro Iwamatsu writel(0x00000B0B, &cpg->frqcrd); 1848d811ca3SNobuhiro Iwamatsu cmp_loop(&cpg->frqcrd, 0x80000000, 0x0); 1858d811ca3SNobuhiro Iwamatsu 1868d811ca3SNobuhiro Iwamatsu /* Clock Init */ 1878d811ca3SNobuhiro Iwamatsu writel(0x00000003, PCLKCR); 1888d811ca3SNobuhiro Iwamatsu writel(0x0000012F, &cpg->vclkcr1); 1898d811ca3SNobuhiro Iwamatsu writel(0x00000119, &cpg->vclkcr2); 1908d811ca3SNobuhiro Iwamatsu writel(0x00000119, &cpg->vclkcr3); 1918d811ca3SNobuhiro Iwamatsu writel(0x00000002, &cpg->zbckcr); 1928d811ca3SNobuhiro Iwamatsu writel(0x00000005, &cpg->flckcr); 1938d811ca3SNobuhiro Iwamatsu writel(0x00000080, &cpg->sd0ckcr); 1948d811ca3SNobuhiro Iwamatsu writel(0x00000080, &cpg->sd1ckcr); 1958d811ca3SNobuhiro Iwamatsu writel(0x00000080, &cpg->sd2ckcr); 1968d811ca3SNobuhiro Iwamatsu writel(0x0000003F, &cpg->fsiackcr); 1978d811ca3SNobuhiro Iwamatsu writel(0x0000003F, &cpg->fsibckcr); 1988d811ca3SNobuhiro Iwamatsu writel(0x00000080, &cpg->subckcr); 1998d811ca3SNobuhiro Iwamatsu writel(0x0000000B, &cpg->spuackcr); 2008d811ca3SNobuhiro Iwamatsu writel(0x0000000B, &cpg->spuvckcr); 2018d811ca3SNobuhiro Iwamatsu writel(0x0000013F, &cpg->msuckcr); 2028d811ca3SNobuhiro Iwamatsu writel(0x00000080, &cpg->hsickcr); 2038d811ca3SNobuhiro Iwamatsu writel(0x0000003F, &cpg->mfck1cr); 2048d811ca3SNobuhiro Iwamatsu writel(0x0000003F, &cpg->mfck2cr); 2058d811ca3SNobuhiro Iwamatsu writel(0x00000107, &cpg->dsitckcr); 2068d811ca3SNobuhiro Iwamatsu writel(0x00000313, &cpg->dsi0pckcr); 2078d811ca3SNobuhiro Iwamatsu writel(0x0000130D, &cpg->dsi1pckcr); 2088d811ca3SNobuhiro Iwamatsu writel(0x2A800E0E, &cpg->dsi0phycr); 2098d811ca3SNobuhiro Iwamatsu writel(0x1E000000, &cpg->pll0cr); 2108d811ca3SNobuhiro Iwamatsu writel(0x2D000000, &cpg->pll0cr); 2118d811ca3SNobuhiro Iwamatsu writel(0x17100000, &cpg->pll1cr); 2128d811ca3SNobuhiro Iwamatsu writel(0x27000080, &cpg->pll2cr); 2138d811ca3SNobuhiro Iwamatsu writel(0x1D000000, &cpg->pll3cr); 2148d811ca3SNobuhiro Iwamatsu writel(0x00080000, &cpg->pll0stpcr); 2158d811ca3SNobuhiro Iwamatsu writel(0x000120C0, &cpg->pll1stpcr); 2168d811ca3SNobuhiro Iwamatsu writel(0x00012000, &cpg->pll2stpcr); 2178d811ca3SNobuhiro Iwamatsu writel(0x00000030, &cpg->pll3stpcr); 2188d811ca3SNobuhiro Iwamatsu 2198d811ca3SNobuhiro Iwamatsu writel(0x0000000B, &cpg->pllecr); 2208d811ca3SNobuhiro Iwamatsu cmp_loop(&cpg->pllecr, 0x00000B00, 0x00000B00); 2218d811ca3SNobuhiro Iwamatsu 2228d811ca3SNobuhiro Iwamatsu writel(0x000120F0, &cpg->dvfscr3); 2238d811ca3SNobuhiro Iwamatsu writel(0x00000020, &cpg->mpmode); 2248d811ca3SNobuhiro Iwamatsu writel(0x0000028A, &cpg->vrefcr); 2258d811ca3SNobuhiro Iwamatsu writel(0xE4628087, &cpg->rmstpcr0); 2268d811ca3SNobuhiro Iwamatsu writel(0xFFFFFFFF, &cpg->rmstpcr1); 2278d811ca3SNobuhiro Iwamatsu writel(0x53FFFFFF, &cpg->rmstpcr2); 2288d811ca3SNobuhiro Iwamatsu writel(0xFFFFFFFF, &cpg->rmstpcr3); 2298d811ca3SNobuhiro Iwamatsu writel(0x00800D3D, &cpg->rmstpcr4); 2308d811ca3SNobuhiro Iwamatsu writel(0xFFFFF3FF, &cpg->rmstpcr5); 2318d811ca3SNobuhiro Iwamatsu writel(0x00000000, &cpg->smstpcr2); 2328d811ca3SNobuhiro Iwamatsu writel(0x00040000, &cpg_srcr->srcr2); 2338d811ca3SNobuhiro Iwamatsu 2348d811ca3SNobuhiro Iwamatsu clrbits_le32(&cpg->pllecr, (1 << 3)); 2358d811ca3SNobuhiro Iwamatsu cmp_loop(&cpg->pllecr, 0x00000800, 0x0); 2368d811ca3SNobuhiro Iwamatsu 2378d811ca3SNobuhiro Iwamatsu writel(0x00000001, &hpb->hpbctrl6); 2388d811ca3SNobuhiro Iwamatsu cmp_loop(&hpb->hpbctrl6, 0x1, 0x1); 2398d811ca3SNobuhiro Iwamatsu 2408d811ca3SNobuhiro Iwamatsu writel(0x00001414, &cpg->frqcrd); 2418d811ca3SNobuhiro Iwamatsu cmp_loop(&cpg->frqcrd, 0x80000000, 0x0); 2428d811ca3SNobuhiro Iwamatsu 2438d811ca3SNobuhiro Iwamatsu writel(0x1d000000, &cpg->pll3cr); 2448d811ca3SNobuhiro Iwamatsu setbits_le32(&cpg->pllecr, (1 << 3)); 2458d811ca3SNobuhiro Iwamatsu cmp_loop(&cpg->pllecr, 0x800, 0x800); 2468d811ca3SNobuhiro Iwamatsu 2478d811ca3SNobuhiro Iwamatsu /* SBSC1 Init*/ 2488d811ca3SNobuhiro Iwamatsu sbsc_init(sbsc1); 2498d811ca3SNobuhiro Iwamatsu 2508d811ca3SNobuhiro Iwamatsu /* SBSC2 Init*/ 2518d811ca3SNobuhiro Iwamatsu sbsc_init(sbsc2); 2528d811ca3SNobuhiro Iwamatsu 2538d811ca3SNobuhiro Iwamatsu writel(0x00000b0b, &cpg->frqcrd); 2548d811ca3SNobuhiro Iwamatsu cmp_loop(&cpg->frqcrd, 0x80000000, 0x0); 255a1263312STetsuyuki Kobayashi writel(0xfffffffc, &cpg->cpgxxcs4); 2568d811ca3SNobuhiro Iwamatsu } 2578d811ca3SNobuhiro Iwamatsu 2588d811ca3SNobuhiro Iwamatsu int board_early_init_f(void) 2598d811ca3SNobuhiro Iwamatsu { 2608d811ca3SNobuhiro Iwamatsu struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE; 2618d811ca3SNobuhiro Iwamatsu struct sh73a0_bsc *bsc = (struct sh73a0_bsc *)BSC_BASE; 2628d811ca3SNobuhiro Iwamatsu struct sh73a0_sbsc_cpg_srcr *cpg_srcr = 2638d811ca3SNobuhiro Iwamatsu (struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE; 2648d811ca3SNobuhiro Iwamatsu 2658d811ca3SNobuhiro Iwamatsu writel(CS0BCR_D, &bsc->cs0bcr); 2668d811ca3SNobuhiro Iwamatsu writel(CS4BCR_D, &bsc->cs4bcr); 2678d811ca3SNobuhiro Iwamatsu writel(CS0WCR_D, &bsc->cs0wcr); 2688d811ca3SNobuhiro Iwamatsu writel(CS4WCR_D, &bsc->cs4wcr); 2698d811ca3SNobuhiro Iwamatsu 2708d811ca3SNobuhiro Iwamatsu clrsetbits_le32(&bsc->cmncr, ~CMNCR_BROMMD, CMNCR_BROMMD); 2718d811ca3SNobuhiro Iwamatsu 2728d811ca3SNobuhiro Iwamatsu clrbits_le32(&cpg->smstpcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); 2738d811ca3SNobuhiro Iwamatsu clrbits_le32(&cpg_srcr->srcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); 274937b6862STetsuyuki Kobayashi clrbits_le32(&cpg->smstpcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1)); 275937b6862STetsuyuki Kobayashi clrbits_le32(&cpg_srcr->srcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1)); 2768d811ca3SNobuhiro Iwamatsu writel(VCLKCR1_D, &cpg->vclkcr1); 2778d811ca3SNobuhiro Iwamatsu 2788d811ca3SNobuhiro Iwamatsu /* Setup SCIF4 / workaround */ 2798d811ca3SNobuhiro Iwamatsu writeb(0x12, PORT32CR); 2808d811ca3SNobuhiro Iwamatsu writeb(0x22, PORT33CR); 2818d811ca3SNobuhiro Iwamatsu writeb(0x12, PORT34CR); 2828d811ca3SNobuhiro Iwamatsu writeb(0x22, PORT35CR); 2838d811ca3SNobuhiro Iwamatsu 2848d811ca3SNobuhiro Iwamatsu return 0; 2858d811ca3SNobuhiro Iwamatsu } 2868d811ca3SNobuhiro Iwamatsu 287f68847faSTetsuyuki Kobayashi void adjust_core_voltage(void) 288f68847faSTetsuyuki Kobayashi { 289f68847faSTetsuyuki Kobayashi u8 data; 290f68847faSTetsuyuki Kobayashi 291f68847faSTetsuyuki Kobayashi data = 0x35; 292f68847faSTetsuyuki Kobayashi i2c_set_bus_num(0); 293f68847faSTetsuyuki Kobayashi i2c_write(0x40, 3, 1, &data, 1); 294f68847faSTetsuyuki Kobayashi } 295f68847faSTetsuyuki Kobayashi 2968d811ca3SNobuhiro Iwamatsu int board_init(void) 2978d811ca3SNobuhiro Iwamatsu { 298f68847faSTetsuyuki Kobayashi adjust_core_voltage(); 2998d811ca3SNobuhiro Iwamatsu sh73a0_pinmux_init(); 3008d811ca3SNobuhiro Iwamatsu 3018d811ca3SNobuhiro Iwamatsu /* SCIFA 4 */ 3028d811ca3SNobuhiro Iwamatsu gpio_request(GPIO_FN_SCIFA4_TXD, NULL); 3038d811ca3SNobuhiro Iwamatsu gpio_request(GPIO_FN_SCIFA4_RXD, NULL); 3048d811ca3SNobuhiro Iwamatsu gpio_request(GPIO_FN_SCIFA4_RTS_, NULL); 3058d811ca3SNobuhiro Iwamatsu gpio_request(GPIO_FN_SCIFA4_CTS_, NULL); 3068d811ca3SNobuhiro Iwamatsu 3078d811ca3SNobuhiro Iwamatsu /* Ethernet/SMSC */ 3088d811ca3SNobuhiro Iwamatsu gpio_request(GPIO_PORT224, NULL); 3098d811ca3SNobuhiro Iwamatsu gpio_direction_input(GPIO_PORT224); 3108d811ca3SNobuhiro Iwamatsu 3118d811ca3SNobuhiro Iwamatsu /* SMSC/USB */ 3128d811ca3SNobuhiro Iwamatsu gpio_request(GPIO_FN_CS4_, NULL); 3138d811ca3SNobuhiro Iwamatsu 3148d811ca3SNobuhiro Iwamatsu /* MMCIF */ 3158d811ca3SNobuhiro Iwamatsu gpio_request(GPIO_FN_MMCCLK0, NULL); 3168d811ca3SNobuhiro Iwamatsu gpio_request(GPIO_FN_MMCCMD0_PU, NULL); 3178d811ca3SNobuhiro Iwamatsu gpio_request(GPIO_FN_MMCD0_0_PU, NULL); 3188d811ca3SNobuhiro Iwamatsu gpio_request(GPIO_FN_MMCD0_1_PU, NULL); 3198d811ca3SNobuhiro Iwamatsu gpio_request(GPIO_FN_MMCD0_2_PU, NULL); 3208d811ca3SNobuhiro Iwamatsu gpio_request(GPIO_FN_MMCD0_3_PU, NULL); 3218d811ca3SNobuhiro Iwamatsu gpio_request(GPIO_FN_MMCD0_4_PU, NULL); 3228d811ca3SNobuhiro Iwamatsu gpio_request(GPIO_FN_MMCD0_5_PU, NULL); 3238d811ca3SNobuhiro Iwamatsu gpio_request(GPIO_FN_MMCD0_6_PU, NULL); 3248d811ca3SNobuhiro Iwamatsu gpio_request(GPIO_FN_MMCD0_7_PU, NULL); 3258d811ca3SNobuhiro Iwamatsu 3268d811ca3SNobuhiro Iwamatsu /* SDHI */ 3278d811ca3SNobuhiro Iwamatsu gpio_request(GPIO_FN_SDHIWP0, NULL); 3288d811ca3SNobuhiro Iwamatsu gpio_request(GPIO_FN_SDHICD0, NULL); 3298d811ca3SNobuhiro Iwamatsu gpio_request(GPIO_FN_SDHICMD0, NULL); 3308d811ca3SNobuhiro Iwamatsu gpio_request(GPIO_FN_SDHICLK0, NULL); 3318d811ca3SNobuhiro Iwamatsu gpio_request(GPIO_FN_SDHID0_3, NULL); 3328d811ca3SNobuhiro Iwamatsu gpio_request(GPIO_FN_SDHID0_2, NULL); 3338d811ca3SNobuhiro Iwamatsu gpio_request(GPIO_FN_SDHID0_1, NULL); 3348d811ca3SNobuhiro Iwamatsu gpio_request(GPIO_FN_SDHID0_0, NULL); 3358d811ca3SNobuhiro Iwamatsu gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL); 3368d811ca3SNobuhiro Iwamatsu gpio_request(GPIO_PORT15, NULL); 3378d811ca3SNobuhiro Iwamatsu gpio_direction_output(GPIO_PORT15, 1); 3388d811ca3SNobuhiro Iwamatsu 3398d811ca3SNobuhiro Iwamatsu /* I2C */ 340650f95b0STetsuyuki Kobayashi gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL); 341650f95b0STetsuyuki Kobayashi gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL); 3428d811ca3SNobuhiro Iwamatsu gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL); 3438d811ca3SNobuhiro Iwamatsu gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL); 3448d811ca3SNobuhiro Iwamatsu 3458d811ca3SNobuhiro Iwamatsu gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); 3468d811ca3SNobuhiro Iwamatsu 3478d811ca3SNobuhiro Iwamatsu return 0; 3488d811ca3SNobuhiro Iwamatsu } 3498d811ca3SNobuhiro Iwamatsu 3508d811ca3SNobuhiro Iwamatsu int dram_init(void) 3518d811ca3SNobuhiro Iwamatsu { 3528d811ca3SNobuhiro Iwamatsu gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 3538d811ca3SNobuhiro Iwamatsu return 0; 3548d811ca3SNobuhiro Iwamatsu } 3558d811ca3SNobuhiro Iwamatsu 3568d811ca3SNobuhiro Iwamatsu int board_eth_init(bd_t *bis) 3578d811ca3SNobuhiro Iwamatsu { 3588d811ca3SNobuhiro Iwamatsu int ret = 0; 3598d811ca3SNobuhiro Iwamatsu #ifdef CONFIG_SMC911X 3608d811ca3SNobuhiro Iwamatsu ret = smc911x_initialize(0, CONFIG_SMC911X_BASE); 3618d811ca3SNobuhiro Iwamatsu #endif 3628d811ca3SNobuhiro Iwamatsu return ret; 3638d811ca3SNobuhiro Iwamatsu } 3648d811ca3SNobuhiro Iwamatsu 3658d811ca3SNobuhiro Iwamatsu void reset_cpu(ulong addr) 3668d811ca3SNobuhiro Iwamatsu { 3674306abdaSTetsuyuki Kobayashi /* Soft Power On Reset */ 3684306abdaSTetsuyuki Kobayashi writel((1 << 31), RESCNT2); 3698d811ca3SNobuhiro Iwamatsu } 370