1*877bfe37SValentin Longchamp /* 2*877bfe37SValentin Longchamp * (C) Copyright 2013 Keymile AG 3*877bfe37SValentin Longchamp * Valentin Longchamp <valentin.longchamp@keymile.com> 4*877bfe37SValentin Longchamp * 5*877bfe37SValentin Longchamp * Copyright 2008-2011 Freescale Semiconductor, Inc. 6*877bfe37SValentin Longchamp * 7*877bfe37SValentin Longchamp * (C) Copyright 2000 8*877bfe37SValentin Longchamp * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9*877bfe37SValentin Longchamp * 10*877bfe37SValentin Longchamp * SPDX-License-Identifier: GPL-2.0+ 11*877bfe37SValentin Longchamp */ 12*877bfe37SValentin Longchamp 13*877bfe37SValentin Longchamp #include <common.h> 14*877bfe37SValentin Longchamp #include <asm/mmu.h> 15*877bfe37SValentin Longchamp 16*877bfe37SValentin Longchamp struct fsl_e_tlb_entry tlb_table[] = { 17*877bfe37SValentin Longchamp /* TLB 0 - for temp stack in cache */ 18*877bfe37SValentin Longchamp SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 19*877bfe37SValentin Longchamp CONFIG_SYS_INIT_RAM_ADDR_PHYS, 20*877bfe37SValentin Longchamp MAS3_SW|MAS3_SR, 0, 21*877bfe37SValentin Longchamp 0, 0, BOOKE_PAGESZ_4K, 0), 22*877bfe37SValentin Longchamp SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 23*877bfe37SValentin Longchamp CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 24*877bfe37SValentin Longchamp MAS3_SW|MAS3_SR, 0, 25*877bfe37SValentin Longchamp 0, 0, BOOKE_PAGESZ_4K, 0), 26*877bfe37SValentin Longchamp SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 27*877bfe37SValentin Longchamp CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 28*877bfe37SValentin Longchamp MAS3_SW|MAS3_SR, 0, 29*877bfe37SValentin Longchamp 0, 0, BOOKE_PAGESZ_4K, 0), 30*877bfe37SValentin Longchamp SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 31*877bfe37SValentin Longchamp CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 32*877bfe37SValentin Longchamp MAS3_SW|MAS3_SR, 0, 33*877bfe37SValentin Longchamp 0, 0, BOOKE_PAGESZ_4K, 0), 34*877bfe37SValentin Longchamp /* TLB 1 */ 35*877bfe37SValentin Longchamp /* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the 36*877bfe37SValentin Longchamp * SRAM is at 0xfff00000, it covered the 0xfffff000. 37*877bfe37SValentin Longchamp */ 38*877bfe37SValentin Longchamp SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, 39*877bfe37SValentin Longchamp MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 40*877bfe37SValentin Longchamp 0, 0, BOOKE_PAGESZ_1M, 1), 41*877bfe37SValentin Longchamp 42*877bfe37SValentin Longchamp /* *I*G* - CCSRBAR */ 43*877bfe37SValentin Longchamp SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 44*877bfe37SValentin Longchamp MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 45*877bfe37SValentin Longchamp 0, 1, BOOKE_PAGESZ_16M, 1), 46*877bfe37SValentin Longchamp /* QRIO */ 47*877bfe37SValentin Longchamp SET_TLB_ENTRY(1, CONFIG_SYS_QRIO_BASE, CONFIG_SYS_QRIO_BASE_PHYS, 48*877bfe37SValentin Longchamp MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 49*877bfe37SValentin Longchamp 0, 2, BOOKE_PAGESZ_64K, 1), 50*877bfe37SValentin Longchamp /* *I*G* - PCI1 */ 51*877bfe37SValentin Longchamp SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 52*877bfe37SValentin Longchamp MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 53*877bfe37SValentin Longchamp 0, 3, BOOKE_PAGESZ_512M, 1), 54*877bfe37SValentin Longchamp /* *I*G* - PCI3 */ 55*877bfe37SValentin Longchamp SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, 56*877bfe37SValentin Longchamp MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 57*877bfe37SValentin Longchamp 0, 4, BOOKE_PAGESZ_512M, 1), 58*877bfe37SValentin Longchamp /* *I*G* - PCI1&3 I/O */ 59*877bfe37SValentin Longchamp SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 60*877bfe37SValentin Longchamp MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 61*877bfe37SValentin Longchamp 0, 6, BOOKE_PAGESZ_128K, 1), 62*877bfe37SValentin Longchamp #ifdef CONFIG_SYS_LBAPP1_BASE_PHYS 63*877bfe37SValentin Longchamp /* LBAPP1 */ 64*877bfe37SValentin Longchamp SET_TLB_ENTRY(1, CONFIG_SYS_LBAPP1_BASE, CONFIG_SYS_LBAPP1_BASE_PHYS, 65*877bfe37SValentin Longchamp MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 66*877bfe37SValentin Longchamp 0, 7, BOOKE_PAGESZ_256M, 1), 67*877bfe37SValentin Longchamp #endif 68*877bfe37SValentin Longchamp #ifdef CONFIG_SYS_LBAPP2_BASE_PHYS 69*877bfe37SValentin Longchamp /* LBAPP2 */ 70*877bfe37SValentin Longchamp SET_TLB_ENTRY(1, CONFIG_SYS_LBAPP2_BASE, CONFIG_SYS_LBAPP2_BASE_PHYS, 71*877bfe37SValentin Longchamp MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 72*877bfe37SValentin Longchamp 0, 8, BOOKE_PAGESZ_256M, 1), 73*877bfe37SValentin Longchamp #endif 74*877bfe37SValentin Longchamp /* Bman/Qman */ 75*877bfe37SValentin Longchamp #ifdef CONFIG_SYS_BMAN_MEM_PHYS 76*877bfe37SValentin Longchamp SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, 77*877bfe37SValentin Longchamp MAS3_SW|MAS3_SR, 0, 78*877bfe37SValentin Longchamp 0, 9, BOOKE_PAGESZ_1M, 1), 79*877bfe37SValentin Longchamp SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, 80*877bfe37SValentin Longchamp CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, 81*877bfe37SValentin Longchamp MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 82*877bfe37SValentin Longchamp 0, 10, BOOKE_PAGESZ_1M, 1), 83*877bfe37SValentin Longchamp #endif 84*877bfe37SValentin Longchamp #ifdef CONFIG_SYS_QMAN_MEM_PHYS 85*877bfe37SValentin Longchamp SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, 86*877bfe37SValentin Longchamp MAS3_SW|MAS3_SR, 0, 87*877bfe37SValentin Longchamp 0, 11, BOOKE_PAGESZ_1M, 1), 88*877bfe37SValentin Longchamp SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, 89*877bfe37SValentin Longchamp CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, 90*877bfe37SValentin Longchamp MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 91*877bfe37SValentin Longchamp 0, 12, BOOKE_PAGESZ_1M, 1), 92*877bfe37SValentin Longchamp #endif 93*877bfe37SValentin Longchamp #ifdef CONFIG_SYS_DCSRBAR_PHYS 94*877bfe37SValentin Longchamp SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, 95*877bfe37SValentin Longchamp MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 96*877bfe37SValentin Longchamp 0, 13, BOOKE_PAGESZ_4M, 1), 97*877bfe37SValentin Longchamp #endif 98*877bfe37SValentin Longchamp #ifdef CONFIG_SYS_NAND_BASE 99*877bfe37SValentin Longchamp /* 100*877bfe37SValentin Longchamp * *I*G - NAND 101*877bfe37SValentin Longchamp * entry 14 and 15 has been used hard coded, they will be disabled 102*877bfe37SValentin Longchamp * in cpu_init_f, so we use entry 16 for nand. 103*877bfe37SValentin Longchamp */ 104*877bfe37SValentin Longchamp SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 105*877bfe37SValentin Longchamp MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 106*877bfe37SValentin Longchamp 0, 16, BOOKE_PAGESZ_32K, 1), 107*877bfe37SValentin Longchamp #endif 108*877bfe37SValentin Longchamp }; 109*877bfe37SValentin Longchamp 110*877bfe37SValentin Longchamp int num_tlb_entries = ARRAY_SIZE(tlb_table); 111