1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2877bfe37SValentin Longchamp /* 3877bfe37SValentin Longchamp * (C) Copyright 2013 Keymile AG 4877bfe37SValentin Longchamp * Valentin Longchamp <valentin.longchamp@keymile.com> 5877bfe37SValentin Longchamp * 6877bfe37SValentin Longchamp * Copyright 2008-2011 Freescale Semiconductor, Inc. 7877bfe37SValentin Longchamp * 8877bfe37SValentin Longchamp * (C) Copyright 2000 9877bfe37SValentin Longchamp * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 10877bfe37SValentin Longchamp */ 11877bfe37SValentin Longchamp 12877bfe37SValentin Longchamp #include <common.h> 13877bfe37SValentin Longchamp #include <asm/mmu.h> 14877bfe37SValentin Longchamp 15877bfe37SValentin Longchamp struct fsl_e_tlb_entry tlb_table[] = { 16877bfe37SValentin Longchamp /* TLB 0 - for temp stack in cache */ 17877bfe37SValentin Longchamp SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 18877bfe37SValentin Longchamp CONFIG_SYS_INIT_RAM_ADDR_PHYS, 19877bfe37SValentin Longchamp MAS3_SW|MAS3_SR, 0, 20877bfe37SValentin Longchamp 0, 0, BOOKE_PAGESZ_4K, 0), 21877bfe37SValentin Longchamp SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 22877bfe37SValentin Longchamp CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 23877bfe37SValentin Longchamp MAS3_SW|MAS3_SR, 0, 24877bfe37SValentin Longchamp 0, 0, BOOKE_PAGESZ_4K, 0), 25877bfe37SValentin Longchamp SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 26877bfe37SValentin Longchamp CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 27877bfe37SValentin Longchamp MAS3_SW|MAS3_SR, 0, 28877bfe37SValentin Longchamp 0, 0, BOOKE_PAGESZ_4K, 0), 29877bfe37SValentin Longchamp SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 30877bfe37SValentin Longchamp CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 31877bfe37SValentin Longchamp MAS3_SW|MAS3_SR, 0, 32877bfe37SValentin Longchamp 0, 0, BOOKE_PAGESZ_4K, 0), 33877bfe37SValentin Longchamp /* TLB 1 */ 34877bfe37SValentin Longchamp /* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the 35877bfe37SValentin Longchamp * SRAM is at 0xfff00000, it covered the 0xfffff000. 36877bfe37SValentin Longchamp */ 37877bfe37SValentin Longchamp SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, 38877bfe37SValentin Longchamp MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 39877bfe37SValentin Longchamp 0, 0, BOOKE_PAGESZ_1M, 1), 40877bfe37SValentin Longchamp 41877bfe37SValentin Longchamp /* *I*G* - CCSRBAR */ 42877bfe37SValentin Longchamp SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 43877bfe37SValentin Longchamp MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 44877bfe37SValentin Longchamp 0, 1, BOOKE_PAGESZ_16M, 1), 45877bfe37SValentin Longchamp /* QRIO */ 46877bfe37SValentin Longchamp SET_TLB_ENTRY(1, CONFIG_SYS_QRIO_BASE, CONFIG_SYS_QRIO_BASE_PHYS, 47877bfe37SValentin Longchamp MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 48877bfe37SValentin Longchamp 0, 2, BOOKE_PAGESZ_64K, 1), 49877bfe37SValentin Longchamp /* *I*G* - PCI1 */ 50877bfe37SValentin Longchamp SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 51877bfe37SValentin Longchamp MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 52877bfe37SValentin Longchamp 0, 3, BOOKE_PAGESZ_512M, 1), 53877bfe37SValentin Longchamp /* *I*G* - PCI3 */ 54877bfe37SValentin Longchamp SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, 55877bfe37SValentin Longchamp MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 56877bfe37SValentin Longchamp 0, 4, BOOKE_PAGESZ_512M, 1), 57877bfe37SValentin Longchamp /* *I*G* - PCI1&3 I/O */ 58877bfe37SValentin Longchamp SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 59877bfe37SValentin Longchamp MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 60877bfe37SValentin Longchamp 0, 6, BOOKE_PAGESZ_128K, 1), 61877bfe37SValentin Longchamp #ifdef CONFIG_SYS_LBAPP1_BASE_PHYS 62877bfe37SValentin Longchamp /* LBAPP1 */ 63877bfe37SValentin Longchamp SET_TLB_ENTRY(1, CONFIG_SYS_LBAPP1_BASE, CONFIG_SYS_LBAPP1_BASE_PHYS, 64877bfe37SValentin Longchamp MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 65877bfe37SValentin Longchamp 0, 7, BOOKE_PAGESZ_256M, 1), 66877bfe37SValentin Longchamp #endif 67877bfe37SValentin Longchamp #ifdef CONFIG_SYS_LBAPP2_BASE_PHYS 68877bfe37SValentin Longchamp /* LBAPP2 */ 69877bfe37SValentin Longchamp SET_TLB_ENTRY(1, CONFIG_SYS_LBAPP2_BASE, CONFIG_SYS_LBAPP2_BASE_PHYS, 70877bfe37SValentin Longchamp MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 71877bfe37SValentin Longchamp 0, 8, BOOKE_PAGESZ_256M, 1), 72877bfe37SValentin Longchamp #endif 73877bfe37SValentin Longchamp /* Bman/Qman */ 74877bfe37SValentin Longchamp #ifdef CONFIG_SYS_BMAN_MEM_PHYS 75877bfe37SValentin Longchamp SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, 76877bfe37SValentin Longchamp MAS3_SW|MAS3_SR, 0, 77877bfe37SValentin Longchamp 0, 9, BOOKE_PAGESZ_1M, 1), 78877bfe37SValentin Longchamp SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, 79877bfe37SValentin Longchamp CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, 80877bfe37SValentin Longchamp MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 81877bfe37SValentin Longchamp 0, 10, BOOKE_PAGESZ_1M, 1), 82877bfe37SValentin Longchamp #endif 83877bfe37SValentin Longchamp #ifdef CONFIG_SYS_QMAN_MEM_PHYS 84877bfe37SValentin Longchamp SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, 85877bfe37SValentin Longchamp MAS3_SW|MAS3_SR, 0, 86877bfe37SValentin Longchamp 0, 11, BOOKE_PAGESZ_1M, 1), 87877bfe37SValentin Longchamp SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, 88877bfe37SValentin Longchamp CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, 89877bfe37SValentin Longchamp MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 90877bfe37SValentin Longchamp 0, 12, BOOKE_PAGESZ_1M, 1), 91877bfe37SValentin Longchamp #endif 92877bfe37SValentin Longchamp #ifdef CONFIG_SYS_DCSRBAR_PHYS 93877bfe37SValentin Longchamp SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, 94877bfe37SValentin Longchamp MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 95877bfe37SValentin Longchamp 0, 13, BOOKE_PAGESZ_4M, 1), 96877bfe37SValentin Longchamp #endif 97877bfe37SValentin Longchamp #ifdef CONFIG_SYS_NAND_BASE 98877bfe37SValentin Longchamp /* 99877bfe37SValentin Longchamp * *I*G - NAND 100877bfe37SValentin Longchamp * entry 14 and 15 has been used hard coded, they will be disabled 101877bfe37SValentin Longchamp * in cpu_init_f, so we use entry 16 for nand. 102877bfe37SValentin Longchamp */ 103877bfe37SValentin Longchamp SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 104877bfe37SValentin Longchamp MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 105877bfe37SValentin Longchamp 0, 16, BOOKE_PAGESZ_32K, 1), 106877bfe37SValentin Longchamp #endif 107877bfe37SValentin Longchamp }; 108877bfe37SValentin Longchamp 109877bfe37SValentin Longchamp int num_tlb_entries = ARRAY_SIZE(tlb_table); 110