1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2013 Keymile AG 4 * Valentin Longchamp <valentin.longchamp@keymile.com> 5 * 6 * Copyright 2009-2011 Freescale Semiconductor, Inc. 7 */ 8 9 #include <common.h> 10 #include <i2c.h> 11 #include <hwconfig.h> 12 #include <asm/mmu.h> 13 #include <fsl_ddr_sdram.h> 14 #include <fsl_ddr_dimm_params.h> 15 16 DECLARE_GLOBAL_DATA_PTR; 17 18 void fsl_ddr_board_options(memctl_options_t *popts, 19 dimm_params_t *pdimm, 20 unsigned int ctrl_num) 21 { 22 if (ctrl_num) { 23 printf("Wrong parameter for controller number %d", ctrl_num); 24 return; 25 } 26 27 /* automatic calibration for nb of cycles between read and DQS pre */ 28 popts->cpo_override = 0xFF; 29 30 /* 1/2 clk delay between wr command and data strobe */ 31 popts->write_data_delay = 4; 32 /* clk lauched 1/2 applied cylcle after address command */ 33 popts->clk_adjust = 4; 34 /* 1T timing: command/address held for only 1 cycle */ 35 popts->twot_en = 0; 36 37 /* we have only one module, half str should be OK */ 38 popts->half_strength_driver_enable = 1; 39 40 /* wrlvl values overridden as recommended by ddr init func */ 41 popts->wrlvl_override = 1; 42 popts->wrlvl_sample = 0xf; 43 popts->wrlvl_start = 0x6; 44 45 /* Enable ZQ calibration */ 46 popts->zq_en = 1; 47 48 /* DHC_EN =1, ODT = 75 Ohm */ 49 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR_ODT_75ohm; 50 } 51 52 int dram_init(void) 53 { 54 phys_size_t dram_size = 0; 55 56 puts("Initializing with SPD\n"); 57 58 dram_size = fsl_ddr_sdram(); 59 60 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 61 dram_size *= 0x100000; 62 63 debug(" DDR: "); 64 gd->ram_size = dram_size; 65 66 return 0; 67 } 68