1# 2# (C) Copyright 2012 3# Stefan Bigler, Keymile AG, stefan.bigler@keymile.com 4# Norbert Mayer, Keymile AG, norbert.mayer@keymile.com 5# Deepak Patel, XENTECH Limited, deepak.patel@xentech.co.uk 6# 7# See file CREDITS for list of people who contributed to this 8# project. 9# 10# This program is free software; you can redistribute it and/or 11# modify it under the terms of the GNU General Public License as 12# published by the Free Software Foundation; either version 2 of 13# the License, or (at your option) any later version. 14# 15# This program is distributed in the hope that it will be useful, 16# but WITHOUT ANY WARRANTY; without even the implied warranty of 17# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18# GNU General Public License for more details. 19# 20# You should have received a copy of the GNU General Public License 21# along with this program; if not, write to the Free Software 22# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 23# MA 02110-1301 USA 24# 25# Refer docs/README.kwimage for more details about how-to configure 26# and create kirkwood boot image 27# 28# This configuration applies to COGE5 design (ARM-part) 29# Two 8-Bit devices are connected on the 16-Bit bus on the same 30# chip-select. The supported devices are 31# MT47H256M8EB-3IT:C 32# MT47H256M8EB-25EIT:C 33 34# Boot Media configurations 35BOOT_FROM spi # Boot from SPI flash 36 37DATA 0xFFD10000 0x01112222 # MPP Control 0 Register 38# bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2]) 39# bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3]) 40# bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4]) 41# bit 15-12: 2, MPPSel3 SPI_MISO (1=NF_IO[5]) 42# bit 19-16: 1, MPPSel4 NF_IO[6] 43# bit 23-20: 1, MPPSel5 NF_IO[7] 44# bit 27-24: 1, MPPSel6 SYSRST_O 45# bit 31-28: 0, MPPSel7 GPO[7] 46 47DATA 0xFFD10004 0x03303300 # MPP Control 1 Register 48# bit 3-0: 0, MPPSel8 GPIO[8] CPU_SDA bitbanged 49# bit 7-4: 0, MPPSel9 GPIO[9] CPU_SCL bitbanged 50# bit 12-8: 3, MPPSel10 UA0_TXD 51# bit 15-12: 3, MPPSel11 UA0_RXD 52# bit 19-16: 0, MPPSel12 not connected 53# bit 23-20: 3, MPPSel13 GPIO[14] 54# bit 27-24: 3, MPPSel14 GPIO[15] 55# bit 31-28: 0, MPPSel15 GPIO[16] BOOT_FL_SEL (SPI-MUX Signal) 56 57DATA 0xFFD10008 0x00001100 # MPP Control 2 Register 58# bit 3-0: 0, MPPSel16 GPIO[16] 59# bit 7-4: 0, MPPSel17 not connected 60# bit 11-8: 1, MPPSel18 NF_IO[0] 61# bit 15-12: 1, MPPSel19 NF_IO[1] 62# bit 19-16: 0, MPPSel20 GPIO[20] 63# bit 23-20: 0, MPPSel21 GPIO[21] 64# bit 27-24: 0, MPPSel22 GPIO[22] 65# bit 31-28: 0, MPPSel23 GPIO[23] 66 67# MPP Control 3-6 Register untouched (MPP24-49) 68 69DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register 70# bit 2-0: 3, Reserved 71# bit 5-3: 3, Reserved 72# bit 6: 0, Reserved 73# bit 7: 0, RGMII-pads voltage = 3.3V 74# bit 10-8: 3, Reserved 75# bit 13-11: 3, Reserved 76# bit 14: 0, Reserved 77# bit 15: 0, MPP RGMII-pads voltage = 3.3V 78# bit 31-16 0x1B1B, Reserved 79 80DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register 81# bit 0-1: 2, Tag RAM RTC RAM0 82# bit 3-2: 1, Tag RAM WTC RAM0 83# bit 7-4: 6, Reserved 84# bit 9-8: 2, Valid RAM RTC RAM 85# bit 11-10: 1, Valid RAM WTC RAM 86# bit 13-12: 2, Dirty RAM RTC RAM 87# bit 15-14: 1, Dirty RAM WTC RAM 88# bit 17-16: 2, Data RAM RTC RAM0 89# bit 19-18: 1, Data RAM WTC RAM0 90# bit 21-20: 2, Data RAM RTC RAM1 91# bit 23-22: 1, Data RAM WTC RAM1 92# bit 25-24: 2, Data RAM RTC RAM2 93# bit 27-26: 1, Data RAM WTC RAM2 94# bit 29-28: 2, Data RAM RTC RAM3 95# bit 31-30: 1, Data RAM WTC RAM4 96 97DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register 98# bit 15-0: ?, Reserved 99# bit 17-16: 2, ECC RAM RTC RAM0 100# bit 19-18: 1, ECC RAM WTC RAM0 101# bit 31-20: ?,Reserved 102 103# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched! 104# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage 105 106# SDRAM initalization 107DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register 108# bit 13-0: 0x4E0, DDR2 clks refresh rate 109# bit 14: 0, reserved 110# bit 15: 0, reserved 111# bit 16: 0, CPU to Dram Write buffer policy 112# bit 17: 0, Enable Registered DIMM or Equivalent Sampling Logic 113# bit 19-18: 0, reserved 114# bit 23-20: 0, reserved 115# bit 24: 1, enable exit self refresh mode on DDR access 116# bit 25: 1, required 117# bit 29-26: 0, reserved 118# bit 31-30: 1, reserved 119 120DATA 0xFFD01404 0x36543000 # DDR Controller Control Low 121# bit 3-0: 0, reserved 122# bit 4: 0, 2T mode =addr/cmd in same cycle 123# bit 5: 0, clk is driven during self refresh, we don't care for APX 124# bit 6: 0, use recommended falling edge of clk for addr/cmd 125# bit 7-11: 0, reserved 126# bit 12-13: 1, reserved, required 1 127# bit 14: 0, input buffer always powered up 128# bit 17-15: 0, reserved 129# bit 18: 1, cpu lock transaction enabled 130# bit 19: 0, reserved 131# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0 132# bit 27-24: 6, CL+1, STARTBURST sample stages, freq 200-399MHz, unbuffer DIMM 133# bit 30-28: 3, required 134# bit 31: 0, no additional STARTBURST delay 135 136DATA 0xFFD01408 0x2202444E # DDR Timing (Low) (active cycles value +1) 137# bit 3-0: 0xe, TRAS = 45ns -> 15 clk cycles 138# bit 7-4: 0x4, TRCD = 15ns -> 5 clk cycles 139# bit 11-8: 0x4, TRP = 15ns -> 5 clk cycles 140# bit 15-12: 0x4, TWR = 15ns -> 5 clk cycles 141# bit 19-16: 0x2, TWTR = 7,5ns -> 3 clk cycles 142# bit 20: 0, extended TRAS msb 143# bit 23-21: 0, reserved 144# bit 27-24: 0x2, TRRD = 7,5ns -> 3 clk cycles 145# bit 31-28: 0x2, TRTP = 7,5ns -> 3 clk cycles 146 147DATA 0xFFD0140C 0x0000003E # DDR Timing (High) 148# bit 6-0: 0x3E, TRFC = 195ns -> 63 clk cycles 149# bit 8-7: 0, TR2R 150# bit 10-9: 0, TR2W 151# bit 12-11: 0, TW2W 152# bit 31-13: 0, reserved 153 154DATA 0xFFD01410 0x00000000 # DDR Address Control 155# bit 1-0: 0, Cs0width=x8 (2 devices) 156# bit 3-2: 0, Cs0size=2Gb 157# bit 5-4: 0, Cs1width=nonexistent 158# bit 7-6: 0, Cs1size =nonexistent 159# bit 9-8: 0, Cs2width=nonexistent 160# bit 11-10: 0, Cs2size =nonexistent 161# bit 13-12: 0, Cs3width=nonexistent 162# bit 15-14: 0, Cs3size =nonexistent 163# bit 16: 0, Cs0AddrSel 164# bit 17: 0, Cs1AddrSel 165# bit 18: 0, Cs2AddrSel 166# bit 19: 0, Cs3AddrSel 167# bit 31-20: 0, required 168 169DATA 0xFFD01414 0x00000000 # DDR Open Pages Control 170# bit 0: 0, OpenPage enabled 171# bit 31-1: 0, required 172 173DATA 0xFFD01418 0x00000000 # DDR Operation 174# bit 3-0: 0, DDR cmd 175# bit 31-4: 0, required 176 177DATA 0xFFD0141C 0x00000652 # DDR Mode 178# bit 2-0: 2, Burst Length = 4 179# bit 3: 0, Burst Type 180# bit 6-4: 5, CAS Latency = 5 181# bit 7: 0, Test mode 182# bit 8: 0, DLL Reset 183# bit 11-9: 3, Write recovery for auto-precharge must be 3 184# bit 12: 0, Active power down exit time, fast exit 185# bit 14-13: 0, reserved 186# bit 31-15: 0, reserved 187 188DATA 0xFFD01420 0x00000006 # DDR Extended Mode 189# bit 0: 0, DDR DLL enabled 190# bit 1: 1, DDR drive strenght reduced 191# bit 2: 1, DDR ODT control lsb, 75ohm termination [RTT0] 192# bit 5-3: 0, required 193# bit 6: 0, DDR ODT control msb, 75ohm termination [RTT1] 194# bit 9-7: 0, required 195# bit 10: 0, differential DQS enabled 196# bit 11: 0, required 197# bit 12: 0, DDR output buffer enabled 198# bit 31-13: 0 required 199 200DATA 0xFFD01424 0x0000F17F # DDR Controller Control High 201# bit 2-0: 7, required 202# bit 3: 1, MBUS Burst Chop disabled 203# bit 6-4: 7, required 204# bit 7: 0, reserved 205# bit 8: 1, add sample stage required for > 266Mhz 206# bit 9: 0, no half clock cycle addition to dataout 207# bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals 208# bit 11: 0, 1/4 clock cycle skew disabled for write mesh 209# bit 15-12:0xf, required 210# bit 31-16: 0, required 211 212DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low 213# bit 3-0: 0, required 214# bit 7-4: 2, M_ODT assertion 2 cycles after read start command 215# bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command 216# (ODT turn off delay 2,5 clk cycles) 217# bit 15-12: 4, internal ODT time based on bit 7-4 218# with the considered SDRAM internal delay 219# bit 19-16: 8, internal ODT de-assertion based on bit 11-8 220# with the considered SDRAM internal delay 221# bit 31-20: 0, required 222 223DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High 224# bit 3-0: 2, M_ODT assertion same as bit 11-8 225# bit 7-4: 5, M_ODT de-assertion same as bit 15-12 226# bit 11-8: 4, internal ODT assertion 2 cycles after write start command 227# with the considered SDRAM internal delay 228# bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command 229# with the considered SDRAM internal delay 230 231DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 232# bit 23-0: 0, reserved 233# bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24] 234 235DATA 0xFFD01504 0x1FFFFFF1 # CS[0]n Size 236# bit 0: 1, Window enabled 237# bit 1: 0, Write Protect disabled 238# bit 3-2: 0, CS0 hit selected 239# bit 23-4:ones, required 240# bit 31-24:0x1F, Size (i.e. 512MB) 241 242DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled 243DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled 244DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled 245 246DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) 247# bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0 248# bit 7-4: 0, ODT0Rd, MODT[1] not asserted 249# bit 11-8: 0, required 250# big 15-11: 0, required 251# bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 252# bit 23-20: 0, ODT0Wr, MODT[1] not asserted 253# bit 27-24: 0, required 254# bit 31-28: 0, required 255 256DATA 0xFFD01498 0x00000004 # DDR ODT Control (High) 257# bit 1-0: 0, ODT0 controlled by ODT Control (low) register above 258# bit 3-2: 1, ODT1 never active 259# bit 31-4: 0, required 260 261DATA 0xFFD0149C 0x0000E801 # CPU ODT Control 262# bit 3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 263# bit 7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0 264# bit 9-8: 0, ODTEn, controlled by ODT0Rd and ODT0Wr 265# bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm 266# bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm 267# bit 14: 1, STARTBURST ODT enabled 268# bit 15: 1, Use ODT Block 269 270DATA 0xFFD01480 0x00000001 # DDR Initialization Control 271# bit 0: 1, enable DDR init upon this register write 272# bit 31-1: 0, reserved 273 274# End of Header extension 275DATA 0x0 0x0 276