1# 2# (C) Copyright 2012 3# Stefan Bigler, Keymile AG, stefan.bigler@keymile.com 4# Norbert Mayer, Keymile AG, norbert.mayer@keymile.com 5# Deepak Patel, XENTECH Limited, deepak.patel@xentech.co.uk 6# 7# SPDX-License-Identifier: GPL-2.0+ 8# 9# Refer doc/README.kwbimage for more details about how-to configure 10# and create kirkwood boot image 11# 12# This configuration applies to COGE5 design (ARM-part) 13# Two 8-Bit devices are connected on the 16-Bit bus on the same 14# chip-select. The supported devices are 15# MT47H256M8EB-3IT:C 16# MT47H256M8EB-25EIT:C 17 18# Boot Media configurations 19BOOT_FROM spi # Boot from SPI flash 20 21DATA 0xFFD10000 0x01112222 # MPP Control 0 Register 22# bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2]) 23# bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3]) 24# bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4]) 25# bit 15-12: 2, MPPSel3 SPI_MISO (1=NF_IO[5]) 26# bit 19-16: 1, MPPSel4 NF_IO[6] 27# bit 23-20: 1, MPPSel5 NF_IO[7] 28# bit 27-24: 1, MPPSel6 SYSRST_O 29# bit 31-28: 0, MPPSel7 GPO[7] 30 31DATA 0xFFD10004 0x03303300 # MPP Control 1 Register 32# bit 3-0: 0, MPPSel8 GPIO[8] CPU_SDA bitbanged 33# bit 7-4: 0, MPPSel9 GPIO[9] CPU_SCL bitbanged 34# bit 12-8: 3, MPPSel10 UA0_TXD 35# bit 15-12: 3, MPPSel11 UA0_RXD 36# bit 19-16: 0, MPPSel12 not connected 37# bit 23-20: 3, MPPSel13 GPIO[14] 38# bit 27-24: 3, MPPSel14 GPIO[15] 39# bit 31-28: 0, MPPSel15 GPIO[16] BOOT_FL_SEL (SPI-MUX Signal) 40 41DATA 0xFFD10008 0x00001100 # MPP Control 2 Register 42# bit 3-0: 0, MPPSel16 GPIO[16] 43# bit 7-4: 0, MPPSel17 not connected 44# bit 11-8: 1, MPPSel18 NF_IO[0] 45# bit 15-12: 1, MPPSel19 NF_IO[1] 46# bit 19-16: 0, MPPSel20 GPIO[20] 47# bit 23-20: 0, MPPSel21 GPIO[21] 48# bit 27-24: 0, MPPSel22 GPIO[22] 49# bit 31-28: 0, MPPSel23 GPIO[23] 50 51# MPP Control 3-6 Register untouched (MPP24-49) 52 53DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register 54# bit 2-0: 3, Reserved 55# bit 5-3: 3, Reserved 56# bit 6: 0, Reserved 57# bit 7: 0, RGMII-pads voltage = 3.3V 58# bit 10-8: 3, Reserved 59# bit 13-11: 3, Reserved 60# bit 14: 0, Reserved 61# bit 15: 0, MPP RGMII-pads voltage = 3.3V 62# bit 31-16 0x1B1B, Reserved 63 64DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register 65# bit 0-1: 2, Tag RAM RTC RAM0 66# bit 3-2: 1, Tag RAM WTC RAM0 67# bit 7-4: 6, Reserved 68# bit 9-8: 2, Valid RAM RTC RAM 69# bit 11-10: 1, Valid RAM WTC RAM 70# bit 13-12: 2, Dirty RAM RTC RAM 71# bit 15-14: 1, Dirty RAM WTC RAM 72# bit 17-16: 2, Data RAM RTC RAM0 73# bit 19-18: 1, Data RAM WTC RAM0 74# bit 21-20: 2, Data RAM RTC RAM1 75# bit 23-22: 1, Data RAM WTC RAM1 76# bit 25-24: 2, Data RAM RTC RAM2 77# bit 27-26: 1, Data RAM WTC RAM2 78# bit 29-28: 2, Data RAM RTC RAM3 79# bit 31-30: 1, Data RAM WTC RAM4 80 81DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register 82# bit 15-0: ?, Reserved 83# bit 17-16: 2, ECC RAM RTC RAM0 84# bit 19-18: 1, ECC RAM WTC RAM0 85# bit 31-20: ?,Reserved 86 87# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched! 88# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage 89 90# SDRAM initalization 91DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register 92# bit 13-0: 0x4E0, DDR2 clks refresh rate 93# bit 14: 0, reserved 94# bit 15: 0, reserved 95# bit 16: 0, CPU to Dram Write buffer policy 96# bit 17: 0, Enable Registered DIMM or Equivalent Sampling Logic 97# bit 19-18: 0, reserved 98# bit 23-20: 0, reserved 99# bit 24: 1, enable exit self refresh mode on DDR access 100# bit 25: 1, required 101# bit 29-26: 0, reserved 102# bit 31-30: 1, reserved 103 104DATA 0xFFD01404 0x36543000 # DDR Controller Control Low 105# bit 3-0: 0, reserved 106# bit 4: 0, 2T mode =addr/cmd in same cycle 107# bit 5: 0, clk is driven during self refresh, we don't care for APX 108# bit 6: 0, use recommended falling edge of clk for addr/cmd 109# bit 7-11: 0, reserved 110# bit 12-13: 1, reserved, required 1 111# bit 14: 0, input buffer always powered up 112# bit 17-15: 0, reserved 113# bit 18: 1, cpu lock transaction enabled 114# bit 19: 0, reserved 115# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0 116# bit 27-24: 6, CL+1, STARTBURST sample stages, freq 200-399MHz, unbuffer DIMM 117# bit 30-28: 3, required 118# bit 31: 0, no additional STARTBURST delay 119 120DATA 0xFFD01408 0x2202444E # DDR Timing (Low) (active cycles value +1) 121# bit 3-0: 0xe, TRAS = 45ns -> 15 clk cycles 122# bit 7-4: 0x4, TRCD = 15ns -> 5 clk cycles 123# bit 11-8: 0x4, TRP = 15ns -> 5 clk cycles 124# bit 15-12: 0x4, TWR = 15ns -> 5 clk cycles 125# bit 19-16: 0x2, TWTR = 7,5ns -> 3 clk cycles 126# bit 20: 0, extended TRAS msb 127# bit 23-21: 0, reserved 128# bit 27-24: 0x2, TRRD = 7,5ns -> 3 clk cycles 129# bit 31-28: 0x2, TRTP = 7,5ns -> 3 clk cycles 130 131DATA 0xFFD0140C 0x0000003E # DDR Timing (High) 132# bit 6-0: 0x3E, TRFC = 195ns -> 63 clk cycles 133# bit 8-7: 0, TR2R 134# bit 10-9: 0, TR2W 135# bit 12-11: 0, TW2W 136# bit 31-13: 0, reserved 137 138DATA 0xFFD01410 0x00000000 # DDR Address Control 139# bit 1-0: 0, Cs0width=x8 (2 devices) 140# bit 3-2: 0, Cs0size=2Gb 141# bit 5-4: 0, Cs1width=nonexistent 142# bit 7-6: 0, Cs1size =nonexistent 143# bit 9-8: 0, Cs2width=nonexistent 144# bit 11-10: 0, Cs2size =nonexistent 145# bit 13-12: 0, Cs3width=nonexistent 146# bit 15-14: 0, Cs3size =nonexistent 147# bit 16: 0, Cs0AddrSel 148# bit 17: 0, Cs1AddrSel 149# bit 18: 0, Cs2AddrSel 150# bit 19: 0, Cs3AddrSel 151# bit 31-20: 0, required 152 153DATA 0xFFD01414 0x00000000 # DDR Open Pages Control 154# bit 0: 0, OpenPage enabled 155# bit 31-1: 0, required 156 157DATA 0xFFD01418 0x00000000 # DDR Operation 158# bit 3-0: 0, DDR cmd 159# bit 31-4: 0, required 160 161DATA 0xFFD0141C 0x00000652 # DDR Mode 162# bit 2-0: 2, Burst Length = 4 163# bit 3: 0, Burst Type 164# bit 6-4: 5, CAS Latency = 5 165# bit 7: 0, Test mode 166# bit 8: 0, DLL Reset 167# bit 11-9: 3, Write recovery for auto-precharge must be 3 168# bit 12: 0, Active power down exit time, fast exit 169# bit 14-13: 0, reserved 170# bit 31-15: 0, reserved 171 172DATA 0xFFD01420 0x00000006 # DDR Extended Mode 173# bit 0: 0, DDR DLL enabled 174# bit 1: 1, DDR drive strenght reduced 175# bit 2: 1, DDR ODT control lsb, 75ohm termination [RTT0] 176# bit 5-3: 0, required 177# bit 6: 0, DDR ODT control msb, 75ohm termination [RTT1] 178# bit 9-7: 0, required 179# bit 10: 0, differential DQS enabled 180# bit 11: 0, required 181# bit 12: 0, DDR output buffer enabled 182# bit 31-13: 0 required 183 184DATA 0xFFD01424 0x0000F17F # DDR Controller Control High 185# bit 2-0: 7, required 186# bit 3: 1, MBUS Burst Chop disabled 187# bit 6-4: 7, required 188# bit 7: 0, reserved 189# bit 8: 1, add sample stage required for > 266Mhz 190# bit 9: 0, no half clock cycle addition to dataout 191# bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals 192# bit 11: 0, 1/4 clock cycle skew disabled for write mesh 193# bit 15-12:0xf, required 194# bit 31-16: 0, required 195 196DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low 197# bit 3-0: 0, required 198# bit 7-4: 2, M_ODT assertion 2 cycles after read start command 199# bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command 200# (ODT turn off delay 2,5 clk cycles) 201# bit 15-12: 4, internal ODT time based on bit 7-4 202# with the considered SDRAM internal delay 203# bit 19-16: 8, internal ODT de-assertion based on bit 11-8 204# with the considered SDRAM internal delay 205# bit 31-20: 0, required 206 207DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High 208# bit 3-0: 2, M_ODT assertion same as bit 11-8 209# bit 7-4: 5, M_ODT de-assertion same as bit 15-12 210# bit 11-8: 4, internal ODT assertion 2 cycles after write start command 211# with the considered SDRAM internal delay 212# bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command 213# with the considered SDRAM internal delay 214 215DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 216# bit 23-0: 0, reserved 217# bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24] 218 219DATA 0xFFD01504 0x1FFFFFF1 # CS[0]n Size 220# bit 0: 1, Window enabled 221# bit 1: 0, Write Protect disabled 222# bit 3-2: 0, CS0 hit selected 223# bit 23-4:ones, required 224# bit 31-24:0x1F, Size (i.e. 512MB) 225 226DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled 227DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled 228DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled 229 230DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) 231# bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0 232# bit 7-4: 0, ODT0Rd, MODT[1] not asserted 233# bit 11-8: 0, required 234# big 15-11: 0, required 235# bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 236# bit 23-20: 0, ODT0Wr, MODT[1] not asserted 237# bit 27-24: 0, required 238# bit 31-28: 0, required 239 240DATA 0xFFD01498 0x00000004 # DDR ODT Control (High) 241# bit 1-0: 0, ODT0 controlled by ODT Control (low) register above 242# bit 3-2: 1, ODT1 never active 243# bit 31-4: 0, required 244 245DATA 0xFFD0149C 0x0000E801 # CPU ODT Control 246# bit 3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 247# bit 7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0 248# bit 9-8: 0, ODTEn, controlled by ODT0Rd and ODT0Wr 249# bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm 250# bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm 251# bit 14: 1, STARTBURST ODT enabled 252# bit 15: 1, Use ODT Block 253 254DATA 0xFFD01480 0x00000001 # DDR Initialization Control 255# bit 0: 1, enable DDR init upon this register write 256# bit 31-1: 0, reserved 257 258# End of Header extension 259DATA 0x0 0x0 260