1# 2# (C) Copyright 2010 3# Heiko Schocher, DENX Software Engineering, hs@denx.de. 4# 5# (C) Copyright 2012 6# Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com 7# Stefan Bigler, Keymile AG, stefan.bigler@keymile.com 8# 9# (C) Copyright 2012 10# See file CREDITS for list of people who contributed to this 11# project. 12# 13# This program is free software; you can redistribute it and/or 14# modify it under the terms of the GNU General Public License as 15# published by the Free Software Foundation; either version 2 of 16# the License, or (at your option) any later version. 17# 18# This program is distributed in the hope that it will be useful, 19# but WITHOUT ANY WARRANTY; without even the implied warranty of 20# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21# GNU General Public License for more details. 22# 23# You should have received a copy of the GNU General Public License 24# along with this program; if not, write to the Free Software 25# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 26# MA 02110-1301 USA 27# 28# Refer doc/README.kwbimage for more details about how-to configure 29# and create kirkwood boot image 30# 31 32# Boot Media configurations 33BOOT_FROM spi # Boot from SPI flash 34 35DATA 0xFFD10000 0x01112222 # MPP Control 0 Register 36# bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2]) 37# bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3]) 38# bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4]) 39# bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5]) 40# bit 19-16: 1, MPPSel4 NF_IO[6] 41# bit 23-20: 1, MPPSel5 NF_IO[7] 42# bit 27-24: 1, MPPSel6 SYSRST_O 43# bit 31-28: 0, MPPSel7 GPO[7] 44 45DATA 0xFFD10004 0x03303300 # MPP Control 1 Register 46# bit 3-0: 0, MPPSel8 GPIO[8] 47# bit 7-4: 0, MPPSel9 GPIO[9] 48# bit 12-8: 3, MPPSel10 UA0_TXD 49# bit 15-12: 3, MPPSel11 UA0_RXD 50# bit 19-16: 0, MPPSel12 not connected 51# bit 23-20: 3, MPPSel13 UA1_TXD 52# bit 27-24: 3, MPPSel14 UA1_RXD 53# bit 31-28: 0, MPPSel15 GPIO[15] 54 55DATA 0xFFD10008 0x00001100 # MPP Control 2 Register 56# bit 3-0: 0, MPPSel16 GPIO[16] 57# bit 7-4: 0, MPPSel17 not connected 58# bit 12-8: 1, MPPSel18 NF_IO[0] 59# bit 15-12: 1, MPPSel19 NF_IO[1] 60# bit 19-16: 0, MPPSel20 GPIO[20] 61# bit 23-20: 0, MPPSel21 GPIO[21] 62# bit 27-24: 0, MPPSel22 GPIO[22] 63# bit 31-28: 0, MPPSel23 GPIO[23] 64 65# MPP Control 3-6 Register untouched (MPP24-49) 66 67DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register 68# bit 2-0: 3, Reserved 69# bit 5-3: 3, Reserved 70# bit 6: 0, Reserved 71# bit 7: 0, RGMII-pads voltage = 3.3V 72# bit 10-8: 3, Reserved 73# bit 13-11: 3, Reserved 74# bit 14: 0, Reserved 75# bit 15: 0, MPP RGMII-pads voltage = 3.3V 76# bit 31-16 0x1B1B, Reserved 77 78DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register 79# bit 0-1: 2, Tag RAM RTC RAM0 80# bit 3-2: 1, Tag RAM WTC RAM0 81# bit 7-4: 6, Reserve 82# bit 9-8: 2, Valid RAM RTC RAM 83# bit 11-10: 1, Valid RAM WTC RAM 84# bit 13-12: 2, Dirty RAM RTC RAM 85# bit 15-14: 1, Dirty RAM WTC RAM 86# bit 17-16: 2, Data RAM RTC RAM0 87# bit 19-18: 1, Data RAM WTC RAM0 88# bit 21-20: 2, Data RAM RTC RAM1 89# bit 23-22: 1, Data RAM WTC RAM1 90# bit 25-24: 2, Data RAM RTC RAM2 91# bit 27-26: 1, Data RAM WTC RAM2 92# bit 29-28: 2, Data RAM RTC RAM3 93# bit 31-30: 1, Data RAM WTC RAM4 94 95DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register 96# bit 15-0: ???, Reserve 97# bit 17-16: 2, ECC RAM RTC RAM0 98# bit 19-18: 1, ECC RAM WTC RAM0 99# bit 31-20: ???,Reserve 100 101# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched! 102# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage 103 104# SDRAM initalization 105DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register 106# bit 13-0: 0x4E0, DDR2 clks refresh rate 107# bit 14: 0, reserved 108# bit 15: 0, reserved 109# bit 16: 0, CPU to Dram Write buffer policy 110# bit 17: 0, Enable Registered DIMM or Equivalent Sampling Logic 111# bit 19-18: 0, reserved 112# bit 23-20: 0, reserved 113# bit 24: 1, enable exit self refresh mode on DDR access 114# bit 25: 1, required 115# bit 29-26: 0, reserved 116# bit 31-30: 1, reserved 117 118DATA 0xFFD01404 0x36543000 # DDR Controller Control Low 119# bit 3-0: 0, reserved 120# bit 4: 0, 2T mode =addr/cmd in same cycle 121# bit 5: 0, clk is driven during self refresh, we don't care for APX 122# bit 6: 0, use recommended falling edge of clk for addr/cmd 123# bit 7-11: 0, reserved 124# bit 12-13: 1, reserved, required 1 125# bit 14: 0, input buffer always powered up 126# bit 17-15: 0, reserved 127# bit 18: 1, cpu lock transaction enabled 128# bit 19: 0, reserved 129# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0 130# bit 27-24: 6, CL+1, STARTBURST sample stages, for freqs 200-399MHz, unbuffered DIMM 131# bit 30-28: 3, required 132# bit 31: 0,no additional STARTBURST delay 133 134DATA 0xFFD01408 0x2302444e # DDR Timing (Low) (active cycles value +1) 135# bit 3-0: 0xE, TRAS, 15 clk (45 ns) 136# bit 7-4: 0x4, TRCD, 5 clk (15 ns) 137# bit 11-8: 0x4, TRP, 5 clk (15 ns) 138# bit 15-12: 0x4, TWR, 5 clk (15 ns) 139# bit 19-16: 0x2, TWTR, 3 clk (7.5 ns) 140# bit 20: 0, extended TRAS msb 141# bit 23-21: 0, reserved 142# bit 27-24: 0x3, TRRD, 4 clk (10 ns) 143# bit 31-28: 0x2, TRTP, 3 clk (7.5 ns) 144 145DATA 0xFFD0140C 0x0000003e # DDR Timing (High) 146# bit 6-0: 0x3E, TRFC, 63 clk (195 ns) 147# bit 8-7: 0, TR2R 148# bit 10-9: 0, TR2W 149# bit 12-11: 0, TW2W 150# bit 31-13: 0, reserved 151 152DATA 0xFFD01410 0x00000001 # DDR Address Control 153# bit 1-0: 1, Cs0width=x16 154# bit 3-2: 0, Cs0size=2Gb 155# bit 5-4: 0, Cs1width=nonexistent 156# bit 7-6: 0, Cs1size =nonexistent 157# bit 9-8: 0, Cs2width=nonexistent 158# bit 11-10: 0, Cs2size =nonexistent 159# bit 13-12: 0, Cs3width=nonexistent 160# bit 15-14: 0, Cs3size =nonexistent 161# bit 16: 0, Cs0AddrSel 162# bit 17: 0, Cs1AddrSel 163# bit 18: 0, Cs2AddrSel 164# bit 19: 0, Cs3AddrSel 165# bit 31-20: 0, required 166 167DATA 0xFFD01414 0x00000000 # DDR Open Pages Control 168# bit 0: 0, OpenPage enabled 169# bit 31-1: 0, required 170 171DATA 0xFFD01418 0x00000000 # DDR Operation 172# bit 3-0: 0, DDR cmd 173# bit 31-4: 0, required 174 175DATA 0xFFD0141C 0x00000652 # DDR Mode 176# bit 2-0: 2, Burst Length = 4 177# bit 3: 0, Burst Type 178# bit 6-4: 5, CAS Latency = 5 179# bit 7: 0, Test mode 180# bit 8: 0, DLL Reset 181# bit 11-9: 3, Write recovery for auto-precharge must be 3 182# bit 12: 0, Active power down exit time, fast exit 183# bit 14-13: 0, reserved 184# bit 31-15: 0, reserved 185 186DATA 0xFFD01420 0x00000006 # DDR Extended Mode 187# bit 0: 0, DDR DLL enabled 188# bit 1: 1, DDR drive strength reduced 189# bit 2: 1, DDR ODT control lsb, 75 ohm termination [RTT0] 190# bit 5-3: 0, required 191# bit 6: 0, DDR ODT control msb, 75 ohm termination [RTT1] 192# bit 9-7: 0, required 193# bit 10: 0, differential DQS enabled 194# bit 11: 0, required 195# bit 12: 0, DDR output buffer enabled 196# bit 31-13: 0 required 197 198DATA 0xFFD01424 0x0000F17F # DDR Controller Control High 199# bit 2-0: 7, required 200# bit 3: 1, MBUS Burst Chop disabled 201# bit 6-4: 7, required 202# bit 7: 0, reserved 203# bit 8: 1, add sample stage required for f > 266 MHz 204# bit 9: 0, no half clock cycle addition to dataout 205# bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals 206# bit 11: 0, 1/4 clock cycle skew disabled for write mesh 207# bit 15-12:0xf, required 208# bit 31-16: 0, required 209 210DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low 211# bit 3-0: 0, required 212# bit 7-4: 2, M_ODT assertion 2 cycles after read start command 213# bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command 214# (ODT turn off delay 2,5 clk cycles) 215# bit 15-12: 4, internal ODT time based on bit 7-4 216# with the considered SDRAM internal delay 217# bit 19-16: 8, internal ODT de-assertion based on bit 11-8 218# with the considered SDRAM internal delay 219# bit 31-20: 0, required 220 221DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High 222# bit 3-0: 2, M_ODT assertion same as bit 11-8 223# bit 7-4: 5, M_ODT de-assertion same as bit 15-12 224# bit 11-8: 4, internal ODT assertion 2 cycles after write start command 225# with the considered SDRAM internal delay 226# bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command 227# with the considered SDRAM internal delay 228 229DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 230# bit 23-0: 0, reserved 231# bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24] 232 233DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size 234# bit 0: 1, Window enabled 235# bit 1: 0, Write Protect disabled 236# bit 3-2: 0, CS0 hit selected 237# bit 23-4:ones, required 238# bit 31-24: 0x0F, Size (i.e. 256MB) 239 240DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled 241DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled 242DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled 243 244DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) 245# bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0 246# bit 7-4: 0, ODT0Rd, MODT[1] not asserted 247# bit 11-8: 0, required 248# big 15-11: 0, required 249# bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 250# bit 23-20: 0, ODT0Wr, MODT[1] not asserted 251# bit 27-24: 0, required 252# bit 31-28: 0, required 253 254DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) 255# bit 1-0: 0, ODT0 controlled by ODT Control (low) register above 256# bit 3-2: 0, ODT1 controlled by register 257# bit 31-4: 0, required 258 259DATA 0xFFD0149C 0x0000E801 # CPU ODT Control 260# bit 3-0: 1, ODTRd, Internal ODT asserted during read from DRAM bank0 261# bit 7-4: 0, ODTWr, Internal ODT not asserted during write to DRAM 262# bit 9-8: 0, ODTEn, controlled by ODTRd and ODTWr 263# bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm 264# bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm 265# bit 14: 1, STARTBURST ODT enabled 266# bit 15: 1, Use ODT Block 267 268DATA 0xFFD01480 0x00000001 # DDR Initialization Control 269# bit 0: 1, enable DDR init upon this register write 270# bit 31-1: 0, reserved 271 272# End of Header extension 273DATA 0x0 0x0 274