1# 2# (C) Copyright 2010 3# Heiko Schocher, DENX Software Engineering, hs@denx.de. 4# 5# (C) Copyright 2012 6# Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com 7# Stefan Bigler, Keymile AG, stefan.bigler@keymile.com 8# 9# (C) Copyright 2012 10# See file CREDITS for list of people who contributed to this 11# project. 12# 13# This program is free software; you can redistribute it and/or 14# modify it under the terms of the GNU General Public License as 15# published by the Free Software Foundation; either version 2 of 16# the License, or (at your option) any later version. 17# 18# This program is distributed in the hope that it will be useful, 19# but WITHOUT ANY WARRANTY; without even the implied warranty of 20# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21# GNU General Public License for more details. 22# 23# You should have received a copy of the GNU General Public License 24# along with this program; if not, write to the Free Software 25# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 26# MA 02110-1301 USA 27# 28# Refer docs/README.kwimage for more details about how-to configure 29# and create kirkwood boot image 30# 31 32# Boot Media configurations 33BOOT_FROM spi # Boot from SPI flash 34 35DATA 0xFFD10000 0x01112222 # MPP Control 0 Register 36# bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2]) 37# bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3]) 38# bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4]) 39# bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5]) 40# bit 19-16: 1, MPPSel4 NF_IO[6] 41# bit 23-20: 1, MPPSel5 NF_IO[7] 42# bit 27-24: 1, MPPSel6 SYSRST_O 43# bit 31-28: 0, MPPSel7 GPO[7] 44 45DATA 0xFFD10004 0x03303300 # MPP Control 1 Register 46# bit 3-0: 0, MPPSel8 GPIO[8] 47# bit 7-4: 0, MPPSel9 GPIO[9] 48# bit 12-8: 3, MPPSel10 UA0_TXD 49# bit 15-12: 3, MPPSel11 UA0_RXD 50# bit 19-16: 0, MPPSel12 not connected 51# bit 23-20: 3, MPPSel13 UA1_TXD 52# bit 27-24: 3, MPPSel14 UA1_RXD 53# bit 31-28: 0, MPPSel15 GPIO[15] 54 55DATA 0xFFD10008 0x00001100 # MPP Control 2 Register 56# bit 3-0: 0, MPPSel16 GPIO[16] 57# bit 7-4: 0, MPPSel17 not connected 58# bit 12-8: 1, MPPSel18 NF_IO[0] 59# bit 15-12: 1, MPPSel19 NF_IO[1] 60# bit 19-16: 0, MPPSel20 GPIO[20] 61# bit 23-20: 0, MPPSel21 GPIO[21] 62# bit 27-24: 0, MPPSel22 GPIO[22] 63# bit 31-28: 0, MPPSel23 GPIO[23] 64 65# MPP Control 3-6 Register untouched (MPP24-49) 66 67DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register 68# bit 2-0: 3, Reserved 69# bit 5-3: 3, Reserved 70# bit 6: 0, Reserved 71# bit 7: 0, RGMII-pads voltage = 3.3V 72# bit 10-8: 3, Reserved 73# bit 13-11: 3, Reserved 74# bit 14: 0, Reserved 75# bit 15: 0, MPP RGMII-pads voltage = 3.3V 76# bit 31-16 0x1B1B, Reserved 77 78DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register 79# bit 0-1: 2, Tag RAM RTC RAM0 80# bit 3-2: 1, Tag RAM WTC RAM0 81# bit 7-4: 6, Reserve 82# bit 9-8: 2, Valid RAM RTC RAM 83# bit 11-10: 1, Valid RAM WTC RAM 84# bit 13-12: 2, Dirty RAM RTC RAM 85# bit 15-14: 1, Dirty RAM WTC RAM 86# bit 17-16: 2, Data RAM RTC RAM0 87# bit 19-18: 1, Data RAM WTC RAM0 88# bit 21-20: 2, Data RAM RTC RAM1 89# bit 23-22: 1, Data RAM WTC RAM1 90# bit 25-24: 2, Data RAM RTC RAM2 91# bit 27-26: 1, Data RAM WTC RAM2 92# bit 29-28: 2, Data RAM RTC RAM3 93# bit 31-30: 1, Data RAM WTC RAM4 94 95DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register 96# bit 15-0: ???, Reserve 97# bit 17-16: 2, ECC RAM RTC RAM0 98# bit 19-18: 1, ECC RAM WTC RAM0 99# bit 31-20: ???,Reserve 100 101DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register 102# bit 23-0: 0x000200, Addr Config tuning 103# bit 31-24: 0, Reserved 104 105# ??? Missing register # CPU RAM Management Control2 Register 106 107DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register 108# bit 15-0: 0x1C00, Opmux Tuning 109# bit 31-16: 0, Pc Dp Tuning 110 111DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register 112# bit 1-0: 1, addr clk tune 113# bit 3-2: 0, reserved 114# bit 5-4: 0, dtcmp clk tune 115# bit 7-6: 0, reserved 116# bit 9-8: 0, macdrv clk tune 117# bit 11-10: 0, opmuxgm2 clk tune 118# bit 15-14: 0, rf clk tune 119# bit 17-16: 0, rfbypass clk tune 120# bit 19-18: 0, pc dp clk tune 121# bit 23-20: 0, icache clk tune 122# bit 27:24: 0, dcache clk tune 123# bit 31:28: 0, regfile tunin 124 125# SDRAM initalization 126DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register 127# bit 13-0: 0x4E0, DDR2 clks refresh rate 128# bit 14: 0, reserved 129# bit 15: 0, reserved 130# bit 16: 0, CPU to Dram Write buffer policy 131# bit 17: 0, Enable Registered DIMM or Equivalent Sampling Logic 132# bit 19-18: 0, reserved 133# bit 23-20: 0, reserved 134# bit 24: 1, enable exit self refresh mode on DDR access 135# bit 25: 1, required 136# bit 29-26: 0, reserved 137# bit 31-30: 1, reserved 138 139DATA 0xFFD01404 0x36543000 # DDR Controller Control Low 140# bit 3-0: 0, reserved 141# bit 4: 0, 2T mode =addr/cmd in same cycle 142# bit 5: 0, clk is driven during self refresh, we don't care for APX 143# bit 6: 0, use recommended falling edge of clk for addr/cmd 144# bit 7-11: 0, reserved 145# bit 12-13: 1, reserved, required 1 146# bit 14: 0, input buffer always powered up 147# bit 17-15: 0, reserved 148# bit 18: 1, cpu lock transaction enabled 149# bit 19: 0, reserved 150# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0 151# bit 27-24: 6, CL+1, STARTBURST sample stages, for freqs 200-399MHz, unbuffered DIMM 152# bit 30-28: 3, required 153# bit 31: 0,no additional STARTBURST delay 154 155DATA 0xFFD01408 0x2302444e # DDR Timing (Low) (active cycles value +1) 156# bit 3-0: 0xE, TRAS, 15 clk (45 ns) 157# bit 7-4: 0x4, TRCD, 5 clk (15 ns) 158# bit 11-8: 0x4, TRP, 5 clk (15 ns) 159# bit 15-12: 0x4, TWR, 5 clk (15 ns) 160# bit 19-16: 0x2, TWTR, 3 clk (7.5 ns) 161# bit 20: 0, extended TRAS msb 162# bit 23-21: 0, reserved 163# bit 27-24: 0x3, TRRD, 4 clk (10 ns) 164# bit 31-28: 0x2, TRTP, 3 clk (7.5 ns) 165 166DATA 0xFFD0140C 0x0000003e # DDR Timing (High) 167# bit 6-0: 0x3E, TRFC, 63 clk (195 ns) 168# bit 8-7: 0, TR2R 169# bit 10-9: 0, TR2W 170# bit 12-11: 0, TW2W 171# bit 31-13: 0, reserved 172 173DATA 0xFFD01410 0x00000001 # DDR Address Control 174# bit 1-0: 1, Cs0width=x16 175# bit 3-2: 0, Cs0size=2Gb 176# bit 5-4: 0, Cs1width=nonexistent 177# bit 7-6: 0, Cs1size =nonexistent 178# bit 9-8: 0, Cs2width=nonexistent 179# bit 11-10: 0, Cs2size =nonexistent 180# bit 13-12: 0, Cs3width=nonexistent 181# bit 15-14: 0, Cs3size =nonexistent 182# bit 16: 0, Cs0AddrSel 183# bit 17: 0, Cs1AddrSel 184# bit 18: 0, Cs2AddrSel 185# bit 19: 0, Cs3AddrSel 186# bit 31-20: 0, required 187 188DATA 0xFFD01414 0x00000000 # DDR Open Pages Control 189# bit 0: 0, OpenPage enabled 190# bit 31-1: 0, required 191 192DATA 0xFFD01418 0x00000000 # DDR Operation 193# bit 3-0: 0, DDR cmd 194# bit 31-4: 0, required 195 196DATA 0xFFD0141C 0x00000652 # DDR Mode 197# bit 2-0: 2, Burst Length = 4 198# bit 3: 0, Burst Type 199# bit 6-4: 5, CAS Latency = 5 200# bit 7: 0, Test mode 201# bit 8: 0, DLL Reset 202# bit 11-9: 3, Write recovery for auto-precharge must be 3 203# bit 12: 0, Active power down exit time, fast exit 204# bit 14-13: 0, reserved 205# bit 31-15: 0, reserved 206 207DATA 0xFFD01420 0x00000006 # DDR Extended Mode 208# bit 0: 0, DDR DLL enabled 209# bit 1: 1, DDR drive strength reduced 210# bit 2: 1, DDR ODT control lsb, 75 ohm termination [RTT0] 211# bit 5-3: 0, required 212# bit 6: 0, DDR ODT control msb, 75 ohm termination [RTT1] 213# bit 9-7: 0, required 214# bit 10: 0, differential DQS enabled 215# bit 11: 0, required 216# bit 12: 0, DDR output buffer enabled 217# bit 31-13: 0 required 218 219DATA 0xFFD01424 0x0000F17F # DDR Controller Control High 220# bit 2-0: 7, required 221# bit 3: 1, MBUS Burst Chop disabled 222# bit 6-4: 7, required 223# bit 7: 0, reserved 224# bit 8: 1, add sample stage required for f > 266 MHz 225# bit 9: 0, no half clock cycle addition to dataout 226# bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals 227# bit 11: 0, 1/4 clock cycle skew disabled for write mesh 228# bit 15-12:0xf, required 229# bit 31-16: 0, required 230 231DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low 232# bit 3-0: 0, required 233# bit 7-4: 2, M_ODT assertion 2 cycles after read start command 234# bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command 235# (ODT turn off delay 2,5 clk cycles) 236# bit 15-12: 4, internal ODT time based on bit 7-4 237# with the considered SDRAM internal delay 238# bit 19-16: 8, internal ODT de-assertion based on bit 11-8 239# with the considered SDRAM internal delay 240# bit 31-20: 0, required 241 242DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High 243# bit 3-0: 2, M_ODT assertion same as bit 11-8 244# bit 7-4: 5, M_ODT de-assertion same as bit 15-12 245# bit 11-8: 4, internal ODT assertion 2 cycles after write start command 246# with the considered SDRAM internal delay 247# bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command 248# with the considered SDRAM internal delay 249 250DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 251# bit 23-0: 0, reserved 252# bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24] 253 254DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size 255# bit 0: 1, Window enabled 256# bit 1: 0, Write Protect disabled 257# bit 3-2: 0, CS0 hit selected 258# bit 23-4:ones, required 259# bit 31-24: 0x0F, Size (i.e. 256MB) 260 261DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled 262DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled 263DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled 264 265DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) 266# bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0 267# bit 7-4: 0, ODT0Rd, MODT[1] not asserted 268# bit 11-8: 0, required 269# big 15-11: 0, required 270# bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 271# bit 23-20: 0, ODT0Wr, MODT[1] not asserted 272# bit 27-24: 0, required 273# bit 31-28: 0, required 274 275DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) 276# bit 1-0: 0, ODT0 controlled by ODT Control (low) register above 277# bit 3-2: 0, ODT1 controlled by register 278# bit 31-4: 0, required 279 280DATA 0xFFD0149C 0x0000E801 # CPU ODT Control 281# bit 3-0: 1, ODTRd, Internal ODT asserted during read from DRAM bank0 282# bit 7-4: 0, ODTWr, Internal ODT not asserted during write to DRAM 283# bit 9-8: 0, ODTEn, controlled by ODTRd and ODTWr 284# bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm 285# bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm 286# bit 14: 1, STARTBURST ODT enabled 287# bit 15: 1, Use ODT Block 288 289DATA 0xFFD01480 0x00000001 # DDR Initialization Control 290# bit 0: 1, enable DDR init upon this register write 291# bit 31-1: 0, reserved 292 293# End of Header extension 294DATA 0x0 0x0 295