1# SPDX-License-Identifier: GPL-2.0+ 2# 3# (C) Copyright 2010 4# Heiko Schocher, DENX Software Engineering, hs@denx.de. 5# Refer doc/README.kwbimage for more details about how-to configure 6# and create kirkwood boot image 7# 8 9# Boot Media configurations 10BOOT_FROM spi # Boot from SPI flash 11 12DATA 0xFFD10000 0x01112222 # MPP Control 0 Register 13# bit 3-0: MPPSel0 2, NF_IO[2] 14# bit 7-4: MPPSel1 2, NF_IO[3] 15# bit 12-8: MPPSel2 2, NF_IO[4] 16# bit 15-12: MPPSel3 2, NF_IO[5] 17# bit 19-16: MPPSel4 1, NF_IO[6] 18# bit 23-20: MPPSel5 1, NF_IO[7] 19# bit 27-24: MPPSel6 1, SYSRST_O 20# bit 31-28: MPPSel7 0, GPO[7] 21 22DATA 0xFFD10004 0x03303300 23 24DATA 0xFFD10008 0x00001100 # MPP Control 2 Register 25# bit 3-0: MPPSel16 0, GPIO[16] 26# bit 7-4: MPPSel17 0, GPIO[17] 27# bit 12-8: MPPSel18 1, NF_IO[0] 28# bit 15-12: MPPSel19 1, NF_IO[1] 29# bit 19-16: MPPSel20 0, GPIO[20] 30# bit 23-20: MPPSel21 0, GPIO[21] 31# bit 27-24: MPPSel22 0, GPIO[22] 32# bit 31-28: MPPSel23 0, GPIO[23] 33 34DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register 35DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register 36DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register 37 38# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched! 39# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage 40 41#Dram initalization 42DATA 0xFFD01400 0x43000400 # SDRAM Configuration Register 43# bit13-0: 0x400 (DDR2 clks refresh rate) 44# bit23-14: zero 45# bit24: 1= enable exit self refresh mode on DDR access 46# bit25: 1 required 47# bit29-26: zero 48# bit31-30: 01 49 50DATA 0xFFD01404 0x39543000 # DDR Controller Control Low 51# bit 3-0: 0 reserved 52# bit 4: 0=addr/cmd in smame cycle 53# bit 5: 0=clk is driven during self refresh, we don't care for APX 54# bit 6: 0=use recommended falling edge of clk for addr/cmd 55# bit14: 0=input buffer always powered up 56# bit18: 1=cpu lock transaction enabled 57# bit23-20: 3=recommended value for CL=3 and STARTBURST_DEL disabled bit31=0 58# bit27-24: 6= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM 59# bit30-28: 3 required 60# bit31: 0=no additional STARTBURST delay 61 62DATA 0xFFD01408 0x34136552 # DDR Timing (Low) (active cycles value +1) 63# bit3-0: TRAS lsbs 64# bit7-4: TRCD 65# bit11- 8: TRP 66# bit15-12: TWR 67# bit19-16: TWTR 68# bit20: TRAS msb 69# bit23-21: 0x0 70# bit27-24: TRRD 71# bit31-28: TRTP 72 73DATA 0xFFD0140C 0x00000033 # DDR Timing (High) 74# bit6-0: TRFC 75# bit8-7: TR2R 76# bit10-9: TR2W 77# bit12-11: TW2W 78# bit31-13: zero required 79 80DATA 0xFFD01410 0x0000000D # DDR Address Control 81# bit1-0: 01, Cs0width=x16 82# bit3-2: 11, Cs0size=1Gb 83# bit5-4: 00, Cs2width=nonexistent 84# bit7-6: 00, Cs1size =nonexistent 85# bit9-8: 00, Cs2width=nonexistent 86# bit11-10: 00, Cs2size =nonexistent 87# bit13-12: 00, Cs3width=nonexistent 88# bit15-14: 00, Cs3size =nonexistent 89# bit16: 0, Cs0AddrSel 90# bit17: 0, Cs1AddrSel 91# bit18: 0, Cs2AddrSel 92# bit19: 0, Cs3AddrSel 93# bit31-20: 0 required 94 95DATA 0xFFD01414 0x00000000 # DDR Open Pages Control 96# bit0: 0, OpenPage enabled 97# bit31-1: 0 required 98 99DATA 0xFFD01418 0x00000000 # DDR Operation 100# bit3-0: 0x0, DDR cmd 101# bit31-4: 0 required 102 103DATA 0xFFD0141C 0x00000652 # DDR Mode 104DATA 0xFFD01420 0x00000044 # DDR Extended Mode 105# bit0: 0, DDR DLL enabled 106# bit1: 0, DDR drive strenght normal 107# bit2: 1, DDR ODT control lsd disabled 108# bit5-3: 000, required 109# bit6: 1, DDR ODT control msb, enabled 110# bit9-7: 000, required 111# bit10: 0, differential DQS enabled 112# bit11: 0, required 113# bit12: 0, DDR output buffer enabled 114# bit31-13: 0 required 115 116DATA 0xFFD01424 0x0000F07F # DDR Controller Control High 117# bit2-0: 111, required 118# bit3 : 1 , MBUS Burst Chop disabled 119# bit6-4: 111, required 120# bit7 : 0 121# bit8 : 0 , no sample stage 122# bit9 : 0 , no half clock cycle addition to dataout 123# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals 124# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh 125# bit15-12: 1111 required 126# bit31-16: 0 required 127DATA 0xFFD01428 0x00074510 128DATA 0xFFD0147c 0x00007451 129 130DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 131DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size 132# bit0: 1, Window enabled 133# bit1: 0, Write Protect disabled 134# bit3-2: 00, CS0 hit selected 135# bit23-4: ones, required 136# bit31-24: 0x07, Size (i.e. 128MB) 137 138DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled 139DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled 140DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled 141 142DATA 0xFFD01494 0x00010001 # DDR ODT Control (Low) 143# bit3-0: 0, ODT0Rd, MODT[0] asserted during read from DRAM CS0 144# bit19-16:0, ODT0Wr, MODT[0] asserted during write to DRAM CS0 145 146DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) 147# bit1-0: 00, ODT0 controlled by ODT Control (low) register above 148# bit3-2: 00, ODT1 controlled by register 149# bit31-4: zero, required 150 151DATA 0xFFD0149C 0x0000FC11 # CPU ODT Control 152# bit3-0: F, ODT0Rd, Internal ODT asserted during read from DRAM bank0 153# bit7-4: 0, ODT0Wr, Internal ODT asserted during write to DRAM bank0 154# bit9-8: 1, ODTEn, never active 155# bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm 156 157DATA 0xFFD01480 0x00000001 # DDR Initialization Control 158# bit0=1, enable DDR init upon this register write 159 160# End of Header extension 161DATA 0x0 0x0 162