1# 2# (C) Copyright 2010 3# Heiko Schocher, DENX Software Engineering, hs@denx.de. 4# 5# (C) Copyright 2011 6# Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com 7# 8# See file CREDITS for list of people who contributed to this 9# project. 10# 11# This program is free software; you can redistribute it and/or 12# modify it under the terms of the GNU General Public License as 13# published by the Free Software Foundation; either version 2 of 14# the License, or (at your option) any later version. 15# 16# This program is distributed in the hope that it will be useful, 17# but WITHOUT ANY WARRANTY; without even the implied warranty of 18# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19# GNU General Public License for more details. 20# 21# You should have received a copy of the GNU General Public License 22# along with this program; if not, write to the Free Software 23# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 24# MA 02110-1301 USA 25# 26# Refer docs/README.kwimage for more details about how-to configure 27# and create kirkwood boot image 28# 29 30# Boot Media configurations 31BOOT_FROM spi # Boot from SPI flash 32 33DATA 0xFFD10000 0x01112222 # MPP Control 0 Register 34# bit 3-0: MPPSel0 2, NF_IO[2] 35# bit 7-4: MPPSel1 2, NF_IO[3] 36# bit 12-8: MPPSel2 2, NF_IO[4] 37# bit 15-12: MPPSel3 2, NF_IO[5] 38# bit 19-16: MPPSel4 1, NF_IO[6] 39# bit 23-20: MPPSel5 1, NF_IO[7] 40# bit 27-24: MPPSel6 1, SYSRST_O 41# bit 31-28: MPPSel7 0, GPO[7] 42 43DATA 0xFFD10004 0x03303300 44 45DATA 0xFFD10008 0x00001100 # MPP Control 2 Register 46# bit 3-0: MPPSel16 0, GPIO[16] 47# bit 7-4: MPPSel17 0, GPIO[17] 48# bit 12-8: MPPSel18 1, NF_IO[0] 49# bit 15-12: MPPSel19 1, NF_IO[1] 50# bit 19-16: MPPSel20 0, GPIO[20] 51# bit 23-20: MPPSel21 0, GPIO[21] 52# bit 27-24: MPPSel22 0, GPIO[22] 53# bit 31-28: MPPSel23 0, GPIO[23] 54 55DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register 56DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register 57DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register 58DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register 59DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register 60DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register 61 62#Dram initalization 63DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register 64# bit13-0: 0x4E0 (DDR2 clks refresh rate) 65# bit23-14: zero 66# bit24: 1= enable exit self refresh mode on DDR access 67# bit25: 1 required 68# bit29-26: zero 69# bit31-30: 01 70 71DATA 0xFFD01404 0x38543000 # DDR Controller Control Low 72# bit 3-0: 0 reserved 73# bit 4: 0=addr/cmd in smame cycle 74# bit 5: 0=clk is driven during self refresh, we don't care for APX 75# bit 6: 0=use recommended falling edge of clk for addr/cmd 76# bit14: 0=input buffer always powered up 77# bit18: 1=cpu lock transaction enabled 78# bit23-20: 5=recommended value for CL=4 and STARTBURST_DEL disabled bit31=0 79# bit27-24: 8= CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM 80# bit30-28: 3 required 81# bit31: 0=no additional STARTBURST delay 82 83DATA 0xFFD01408 0x2302433E # DDR Timing (Low) (active cycles value +1) 84# bit3-0: TRAS lsbs 85# bit7-4: TRCD 86# bit11- 8: TRP 87# bit15-12: TWR 88# bit19-16: TWTR 89# bit20: TRAS msb 90# bit23-21: 0x0 91# bit27-24: TRRD 92# bit31-28: TRTP 93 94DATA 0xFFD0140C 0x00000A3E # DDR Timing (High) 95# bit6-0: TRFC 96# bit8-7: TR2R 97# bit10-9: TR2W 98# bit12-11: TW2W 99# bit31-13: zero required 100 101DATA 0xFFD01410 0x00000001 # DDR Address Control 102# bit1-0: 01, Cs0width=x16 103# bit3-2: 00, Cs0size=2Gb 104# bit5-4: 00, Cs2width=nonexistent 105# bit7-6: 00, Cs1size =nonexistent 106# bit9-8: 00, Cs2width=nonexistent 107# bit11-10: 00, Cs2size =nonexistent 108# bit13-12: 00, Cs3width=nonexistent 109# bit15-14: 00, Cs3size =nonexistent 110# bit16: 0, Cs0AddrSel 111# bit17: 0, Cs1AddrSel 112# bit18: 0, Cs2AddrSel 113# bit19: 0, Cs3AddrSel 114# bit31-20: 0 required 115 116DATA 0xFFD01414 0x00000000 # DDR Open Pages Control 117# bit0: 0, OpenPage enabled 118# bit31-1: 0 required 119 120DATA 0xFFD01418 0x00000000 # DDR Operation 121# bit3-0: 0x0, DDR cmd 122# bit31-4: 0 required 123 124DATA 0xFFD0141C 0x00000652 # DDR Mode 125DATA 0xFFD01420 0x00000006 # DDR Extended Mode 126# bit0: 0, DDR DLL enabled 127# bit1: 1, DDR drive strenght reduced 128# bit2: 1, DDR ODT control lsd disabled 129# bit5-3: 000, required 130# bit6: 0, DDR ODT control msb disabled 131# bit9-7: 000, required 132# bit10: 0, differential DQS enabled 133# bit11: 0, required 134# bit12: 0, DDR output buffer enabled 135# bit31-13: 0 required 136 137DATA 0xFFD01424 0x0000F17F # DDR Controller Control High 138# bit2-0: 111, required 139# bit3 : 1 , MBUS Burst Chop disabled 140# bit6-4: 111, required 141# bit7 : 0 142# bit8 : 1 , add a sample stage 143# bit9 : 0 , no half clock cycle addition to dataout 144# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals 145# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh 146# bit15-12: 1111 required 147# bit31-16: 0 required 148 149DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low 150# bit3-0 : 0000, required 151# bit7-4 : 0010, M_ODT assertion 2 cycles after read 152# bit11-8 : 1001, M_ODT de-assertion 5 cycles after read 153# bit15-12: 0100, internal ODT assertion 4 cycles after read 154# bit19-16: 1000, internal ODT de-assertion 8 cycles after read 155# bit31-20: 0 , required 156 157DATA 0xFFD0147c 0x00008451 # DDR2 SDRAM Timing High 158# bit3-0 : 0001, M_ODT assertion same cycle as write 159# bit7-4 : 0101, M_ODT de-assertion x cycles after write 160# bit11-8 : 0100, internal ODT assertion x cycles after write 161# bit15-12: 1000, internal ODT de-assertion x cycles after write 162 163DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 164DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size 165# bit0: 1, Window enabled 166# bit1: 0, Write Protect disabled 167# bit3-2: 00, CS0 hit selected 168# bit23-4: ones, required 169# bit31-24: 0x0F, Size (i.e. 256MB) 170 171DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled 172DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled 173DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled 174 175DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) 176# bit3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0 177# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 178 179DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) 180# bit1-0: 00, ODT0 controlled by ODT Control (low) register above 181# bit3-2: 00, ODT1 controlled by register 182# bit31-4: zero, required 183 184DATA 0xFFD0149C 0x0000F801 # CPU ODT Control 185# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 186# bit7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0 187# bit9-8: 0, ODTEn, controlled by ODT0Rd and ODT0Wr 188# bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm 189# bit13-12:3, STARTBURST ODT buffer selected, 50 ohm 190# bit14 :1, STARTBURST ODT enabled 191# bit15 :1, Use ODT Block 192 193DATA 0xFFD01480 0x00000001 # DDR Initialization Control 194# bit0=1, enable DDR init upon this register write 195 196# End of Header extension 197DATA 0x0 0x0 198