1# 2# (C) Copyright 2010 3# Heiko Schocher, DENX Software Engineering, hs@denx.de. 4# 5# (C) Copyright 2011 6# Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com 7# 8# SPDX-License-Identifier: GPL-2.0+ 9# 10# Refer doc/README.kwbimage for more details about how-to configure 11# and create kirkwood boot image 12# 13 14# Boot Media configurations 15BOOT_FROM spi # Boot from SPI flash 16 17DATA 0xFFD10000 0x01112222 # MPP Control 0 Register 18# bit 3-0: MPPSel0 2, NF_IO[2] 19# bit 7-4: MPPSel1 2, NF_IO[3] 20# bit 12-8: MPPSel2 2, NF_IO[4] 21# bit 15-12: MPPSel3 2, NF_IO[5] 22# bit 19-16: MPPSel4 1, NF_IO[6] 23# bit 23-20: MPPSel5 1, NF_IO[7] 24# bit 27-24: MPPSel6 1, SYSRST_O 25# bit 31-28: MPPSel7 0, GPO[7] 26 27DATA 0xFFD10004 0x03303300 28 29DATA 0xFFD10008 0x00001100 # MPP Control 2 Register 30# bit 3-0: MPPSel16 0, GPIO[16] 31# bit 7-4: MPPSel17 0, GPIO[17] 32# bit 12-8: MPPSel18 1, NF_IO[0] 33# bit 15-12: MPPSel19 1, NF_IO[1] 34# bit 19-16: MPPSel20 0, GPIO[20] 35# bit 23-20: MPPSel21 0, GPIO[21] 36# bit 27-24: MPPSel22 0, GPIO[22] 37# bit 31-28: MPPSel23 0, GPIO[23] 38 39DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register 40DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register 41DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register 42 43# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched! 44# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage 45 46#Dram initalization 47DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register 48# bit13-0: 0x4E0 (DDR2 clks refresh rate) 49# bit23-14: zero 50# bit24: 1= enable exit self refresh mode on DDR access 51# bit25: 1 required 52# bit29-26: zero 53# bit31-30: 01 54 55DATA 0xFFD01404 0x38543000 # DDR Controller Control Low 56# bit 3-0: 0 reserved 57# bit 4: 0=addr/cmd in smame cycle 58# bit 5: 0=clk is driven during self refresh, we don't care for APX 59# bit 6: 0=use recommended falling edge of clk for addr/cmd 60# bit14: 0=input buffer always powered up 61# bit18: 1=cpu lock transaction enabled 62# bit23-20: 5=recommended value for CL=4 and STARTBURST_DEL disabled bit31=0 63# bit27-24: 8= CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM 64# bit30-28: 3 required 65# bit31: 0=no additional STARTBURST delay 66 67DATA 0xFFD01408 0x2302433E # DDR Timing (Low) (active cycles value +1) 68# bit3-0: TRAS lsbs 69# bit7-4: TRCD 70# bit11- 8: TRP 71# bit15-12: TWR 72# bit19-16: TWTR 73# bit20: TRAS msb 74# bit23-21: 0x0 75# bit27-24: TRRD 76# bit31-28: TRTP 77 78DATA 0xFFD0140C 0x00000A3E # DDR Timing (High) 79# bit6-0: TRFC 80# bit8-7: TR2R 81# bit10-9: TR2W 82# bit12-11: TW2W 83# bit31-13: zero required 84 85DATA 0xFFD01410 0x00000001 # DDR Address Control 86# bit1-0: 01, Cs0width=x16 87# bit3-2: 00, Cs0size=2Gb 88# bit5-4: 00, Cs2width=nonexistent 89# bit7-6: 00, Cs1size =nonexistent 90# bit9-8: 00, Cs2width=nonexistent 91# bit11-10: 00, Cs2size =nonexistent 92# bit13-12: 00, Cs3width=nonexistent 93# bit15-14: 00, Cs3size =nonexistent 94# bit16: 0, Cs0AddrSel 95# bit17: 0, Cs1AddrSel 96# bit18: 0, Cs2AddrSel 97# bit19: 0, Cs3AddrSel 98# bit31-20: 0 required 99 100DATA 0xFFD01414 0x00000000 # DDR Open Pages Control 101# bit0: 0, OpenPage enabled 102# bit31-1: 0 required 103 104DATA 0xFFD01418 0x00000000 # DDR Operation 105# bit3-0: 0x0, DDR cmd 106# bit31-4: 0 required 107 108DATA 0xFFD0141C 0x00000652 # DDR Mode 109DATA 0xFFD01420 0x00000006 # DDR Extended Mode 110# bit0: 0, DDR DLL enabled 111# bit1: 1, DDR drive strenght reduced 112# bit2: 1, DDR ODT control lsd disabled 113# bit5-3: 000, required 114# bit6: 0, DDR ODT control msb disabled 115# bit9-7: 000, required 116# bit10: 0, differential DQS enabled 117# bit11: 0, required 118# bit12: 0, DDR output buffer enabled 119# bit31-13: 0 required 120 121DATA 0xFFD01424 0x0000F17F # DDR Controller Control High 122# bit2-0: 111, required 123# bit3 : 1 , MBUS Burst Chop disabled 124# bit6-4: 111, required 125# bit7 : 0 126# bit8 : 1 , add a sample stage 127# bit9 : 0 , no half clock cycle addition to dataout 128# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals 129# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh 130# bit15-12: 1111 required 131# bit31-16: 0 required 132 133DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low 134# bit3-0 : 0000, required 135# bit7-4 : 0010, M_ODT assertion 2 cycles after read 136# bit11-8 : 0101, M_ODT de-assertion 5 cycles after read 137# bit15-12: 0100, internal ODT assertion 4 cycles after read 138# bit19-16: 1000, internal ODT de-assertion 8 cycles after read 139# bit31-20: 0 , required 140 141DATA 0xFFD0147c 0x00008451 # DDR2 SDRAM Timing High 142# bit3-0 : 0001, M_ODT assertion same cycle as write 143# bit7-4 : 0101, M_ODT de-assertion x cycles after write 144# bit11-8 : 0100, internal ODT assertion x cycles after write 145# bit15-12: 1000, internal ODT de-assertion x cycles after write 146 147DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 148DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size 149# bit0: 1, Window enabled 150# bit1: 0, Write Protect disabled 151# bit3-2: 00, CS0 hit selected 152# bit23-4: ones, required 153# bit31-24: 0x0F, Size (i.e. 256MB) 154 155DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled 156DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled 157DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled 158 159DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) 160# bit3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0 161# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 162 163DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) 164# bit1-0: 00, ODT0 controlled by ODT Control (low) register above 165# bit3-2: 00, ODT1 controlled by register 166# bit31-4: zero, required 167 168DATA 0xFFD0149C 0x0000F801 # CPU ODT Control 169# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 170# bit7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0 171# bit9-8: 0, ODTEn, controlled by ODT0Rd and ODT0Wr 172# bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm 173# bit13-12:3, STARTBURST ODT buffer selected, 50 ohm 174# bit14 :1, STARTBURST ODT enabled 175# bit15 :1, Use ODT Block 176 177DATA 0xFFD01480 0x00000001 # DDR Initialization Control 178# bit0=1, enable DDR init upon this register write 179 180# End of Header extension 181DATA 0x0 0x0 182