1 /* 2 * (C) Copyright 2009 3 * Marvell Semiconductor <www.marvell.com> 4 * Prafulla Wadaskar <prafulla@marvell.com> 5 * 6 * (C) Copyright 2009 7 * Stefan Roese, DENX Software Engineering, sr@denx.de. 8 * 9 * (C) Copyright 2010 10 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 28 * MA 02110-1301 USA 29 */ 30 31 #include <common.h> 32 #include <i2c.h> 33 #include <nand.h> 34 #include <netdev.h> 35 #include <miiphy.h> 36 #include <spi.h> 37 #include <asm/io.h> 38 #include <asm/arch/cpu.h> 39 #include <asm/arch/kirkwood.h> 40 #include <asm/arch/mpp.h> 41 42 #include "../common/common.h" 43 44 DECLARE_GLOBAL_DATA_PTR; 45 46 /* 47 * BOCO FPGA definitions 48 */ 49 #define BOCO 0x10 50 #define REG_CTRL_H 0x02 51 #define MASK_WRL_UNITRUN 0x01 52 #define MASK_RBX_PGY_PRESENT 0x40 53 #define REG_IRQ_CIRQ2 0x2d 54 #define MASK_RBI_DEFECT_16 0x01 55 56 /* Multi-Purpose Pins Functionality configuration */ 57 u32 kwmpp_config[] = { 58 MPP0_NF_IO2, 59 MPP1_NF_IO3, 60 MPP2_NF_IO4, 61 MPP3_NF_IO5, 62 MPP4_NF_IO6, 63 MPP5_NF_IO7, 64 MPP6_SYSRST_OUTn, 65 MPP7_PEX_RST_OUTn, 66 #if defined(CONFIG_SOFT_I2C) 67 MPP8_GPIO, /* SDA */ 68 MPP9_GPIO, /* SCL */ 69 #endif 70 #if defined(CONFIG_HARD_I2C) 71 MPP8_TW_SDA, 72 MPP9_TW_SCK, 73 #endif 74 MPP10_UART0_TXD, 75 MPP11_UART0_RXD, 76 MPP12_GPO, /* Reserved */ 77 MPP13_UART1_TXD, 78 MPP14_UART1_RXD, 79 MPP15_GPIO, /* Not used */ 80 MPP16_GPIO, /* Not used */ 81 MPP17_GPIO, /* Reserved */ 82 MPP18_NF_IO0, 83 MPP19_NF_IO1, 84 MPP20_GPIO, 85 MPP21_GPIO, 86 MPP22_GPIO, 87 MPP23_GPIO, 88 MPP24_GPIO, 89 MPP25_GPIO, 90 MPP26_GPIO, 91 MPP27_GPIO, 92 MPP28_GPIO, 93 MPP29_GPIO, 94 MPP30_GPIO, 95 MPP31_GPIO, 96 MPP32_GPIO, 97 MPP33_GPIO, 98 MPP34_GPIO, /* CDL1 (input) */ 99 MPP35_GPIO, /* CDL2 (input) */ 100 MPP36_GPIO, /* MAIN_IRQ (input) */ 101 MPP37_GPIO, /* BOARD_LED */ 102 MPP38_GPIO, /* Piggy3 LED[1] */ 103 MPP39_GPIO, /* Piggy3 LED[2] */ 104 MPP40_GPIO, /* Piggy3 LED[3] */ 105 MPP41_GPIO, /* Piggy3 LED[4] */ 106 MPP42_GPIO, /* Piggy3 LED[5] */ 107 MPP43_GPIO, /* Piggy3 LED[6] */ 108 MPP44_GPIO, /* Piggy3 LED[7], BIST_EN_L */ 109 MPP45_GPIO, /* Piggy3 LED[8] */ 110 MPP46_GPIO, /* Reserved */ 111 MPP47_GPIO, /* Reserved */ 112 MPP48_GPIO, /* Reserved */ 113 MPP49_GPIO, /* SW_INTOUTn */ 114 0 115 }; 116 117 #if defined(CONFIG_KM_MGCOGE3UN) 118 /* 119 * Wait for startup OK from mgcoge3ne 120 */ 121 int startup_allowed(void) 122 { 123 unsigned char buf; 124 125 /* 126 * Read CIRQ16 bit (bit 0) 127 */ 128 if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0) 129 printf("%s: Error reading Boco\n", __func__); 130 else 131 if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16) 132 return 1; 133 return 0; 134 } 135 #endif 136 137 #if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352)) 138 /* 139 * All boards with PIGGY4 connected via a simple switch have ethernet always 140 * present. 141 */ 142 int ethernet_present(void) 143 { 144 return 1; 145 } 146 #else 147 int ethernet_present(void) 148 { 149 uchar buf; 150 int ret = 0; 151 152 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { 153 printf("%s: Error reading Boco\n", __func__); 154 return -1; 155 } 156 if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT) 157 ret = 1; 158 159 return ret; 160 } 161 #endif 162 163 int initialize_unit_leds(void) 164 { 165 /* 166 * Init the unit LEDs per default they all are 167 * ok apart from bootstat 168 */ 169 uchar buf; 170 171 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { 172 printf("%s: Error reading Boco\n", __func__); 173 return -1; 174 } 175 buf |= MASK_WRL_UNITRUN; 176 if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { 177 printf("%s: Error writing Boco\n", __func__); 178 return -1; 179 } 180 return 0; 181 } 182 183 #if defined(CONFIG_BOOTCOUNT_LIMIT) 184 void set_bootcount_addr(void) 185 { 186 uchar buf[32]; 187 unsigned int bootcountaddr; 188 bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR; 189 sprintf((char *)buf, "0x%x", bootcountaddr); 190 setenv("bootcountaddr", (char *)buf); 191 } 192 #endif 193 194 int misc_init_r(void) 195 { 196 char *str; 197 int mach_type; 198 199 str = getenv("mach_type"); 200 if (str != NULL) { 201 mach_type = simple_strtoul(str, NULL, 10); 202 printf("Overwriting MACH_TYPE with %d!!!\n", mach_type); 203 gd->bd->bi_arch_number = mach_type; 204 } 205 #if defined(CONFIG_KM_MGCOGE3UN) 206 char *wait_for_ne; 207 wait_for_ne = getenv("waitforne"); 208 if (wait_for_ne != NULL) { 209 if (strcmp(wait_for_ne, "true") == 0) { 210 int cnt = 0; 211 int abort = 0; 212 puts("NE go: "); 213 while (startup_allowed() == 0) { 214 if (tstc()) { 215 (void) getc(); /* consume input */ 216 abort = 1; 217 break; 218 } 219 udelay(200000); 220 cnt++; 221 if (cnt == 5) 222 puts("wait\b\b\b\b"); 223 if (cnt == 10) { 224 cnt = 0; 225 puts(" \b\b\b\b"); 226 } 227 } 228 if (abort == 1) 229 printf("\nAbort waiting for ne\n"); 230 else 231 puts("OK\n"); 232 } 233 } 234 #endif 235 236 initialize_unit_leds(); 237 set_km_env(); 238 #if defined(CONFIG_BOOTCOUNT_LIMIT) 239 set_bootcount_addr(); 240 #endif 241 return 0; 242 } 243 244 int board_early_init_f(void) 245 { 246 u32 tmp; 247 248 kirkwood_mpp_conf(kwmpp_config, NULL); 249 250 /* 251 * The FLASH_GPIO_PIN switches between using a 252 * NAND or a SPI FLASH. Set this pin on start 253 * to NAND mode. 254 */ 255 tmp = readl(KW_GPIO0_BASE); 256 writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE); 257 tmp = readl(KW_GPIO0_BASE + 4); 258 writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4); 259 260 #if defined(CONFIG_SOFT_I2C) 261 /* init the GPIO for I2C Bitbang driver */ 262 kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1); 263 kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1); 264 kw_gpio_direction_output(KM_KIRKWOOD_SDA_PIN, 0); 265 kw_gpio_direction_output(KM_KIRKWOOD_SCL_PIN, 0); 266 #endif 267 #if defined(CONFIG_SYS_EEPROM_WREN) 268 kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38); 269 kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1); 270 #endif 271 #if defined(CONFIG_KM_RECONFIG_XLX) 272 /* trigger the reconfiguration of the xilinx fpga */ 273 kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1); 274 kw_gpio_direction_output(KM_XLX_PROGRAM_B_PIN, 0); 275 kw_gpio_direction_input(KM_XLX_PROGRAM_B_PIN); 276 #endif 277 return 0; 278 } 279 280 int board_init(void) 281 { 282 /* address of boot parameters */ 283 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; 284 285 return 0; 286 } 287 288 int board_spi_claim_bus(struct spi_slave *slave) 289 { 290 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0); 291 292 return 0; 293 } 294 295 void board_spi_release_bus(struct spi_slave *slave) 296 { 297 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1); 298 } 299 300 int dram_init(void) 301 { 302 /* dram_init must store complete ramsize in gd->ram_size */ 303 /* Fix this */ 304 gd->ram_size = get_ram_size((void *)kw_sdram_bar(0), 305 kw_sdram_bs(0)); 306 return 0; 307 } 308 309 void dram_init_banksize(void) 310 { 311 int i; 312 313 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 314 gd->bd->bi_dram[i].start = kw_sdram_bar(i); 315 gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i), 316 kw_sdram_bs(i)); 317 } 318 } 319 320 #if (defined(CONFIG_KM_MGCOGE3UN)|defined(CONFIG_PORTL2)) 321 322 #define PHY_LED_SEL 0x18 323 #define PHY_LED0_LINK (0x5) 324 #define PHY_LED1_ACT (0x8<<4) 325 #define PHY_LED2_INT (0xe<<8) 326 #define PHY_SPEC_CTRL 0x1c 327 #define PHY_RGMII_CLK_STABLE (0x1<<10) 328 #define PHY_CLSA (0x1<<1) 329 330 /* Configure and enable MV88E3018 PHY */ 331 void reset_phy(void) 332 { 333 char *name = "egiga0"; 334 unsigned short reg; 335 336 if (miiphy_set_current_dev(name)) 337 return; 338 339 /* RGMII clk transition on data stable */ 340 if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, ®) != 0) 341 printf("Error reading PHY spec ctrl reg\n"); 342 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, 343 reg | PHY_RGMII_CLK_STABLE | PHY_CLSA) != 0) 344 printf("Error writing PHY spec ctrl reg\n"); 345 346 /* leds setup */ 347 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL, 348 PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT) != 0) 349 printf("Error writing PHY LED reg\n"); 350 351 /* reset the phy */ 352 miiphy_reset(name, CONFIG_PHY_BASE_ADR); 353 } 354 #else 355 /* Configure and enable MV88E1118 PHY on the piggy*/ 356 void reset_phy(void) 357 { 358 char *name = "egiga0"; 359 360 if (miiphy_set_current_dev(name)) 361 return; 362 363 /* reset the phy */ 364 miiphy_reset(name, CONFIG_PHY_BASE_ADR); 365 } 366 #endif 367 368 369 #if defined(CONFIG_HUSH_INIT_VAR) 370 int hush_init_var(void) 371 { 372 ivm_read_eeprom(); 373 return 0; 374 } 375 #endif 376 377 #if defined(CONFIG_BOOTCOUNT_LIMIT) 378 const ulong patterns[] = { 0x00000000, 379 0xFFFFFFFF, 380 0xFF00FF00, 381 0x0F0F0F0F, 382 0xF0F0F0F0}; 383 const ulong NBR_OF_PATTERNS = ARRAY_SIZE(patterns); 384 const ulong OFFS_PATTERN = 3; 385 const ulong REPEAT_PATTERN = 1000; 386 387 void bootcount_store(ulong a) 388 { 389 ulong *save_addr; 390 ulong size = 0; 391 int i; 392 393 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 394 size += gd->bd->bi_dram[i].size; 395 save_addr = (ulong *)(size - BOOTCOUNT_ADDR); 396 writel(a, save_addr); 397 writel(BOOTCOUNT_MAGIC, &save_addr[1]); 398 399 for (i = 0; i < REPEAT_PATTERN; i++) 400 writel(patterns[i % NBR_OF_PATTERNS], 401 &save_addr[i+OFFS_PATTERN]); 402 403 } 404 405 ulong bootcount_load(void) 406 { 407 ulong *save_addr; 408 ulong size = 0; 409 ulong counter = 0; 410 int i, tmp; 411 412 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 413 size += gd->bd->bi_dram[i].size; 414 save_addr = (ulong *)(size - BOOTCOUNT_ADDR); 415 416 counter = readl(&save_addr[0]); 417 418 /* Is the counter reliable, check in the big pattern for bit errors */ 419 for (i = 0; (i < REPEAT_PATTERN) && (counter != 0); i++) { 420 tmp = readl(&save_addr[i+OFFS_PATTERN]); 421 if (tmp != patterns[i % NBR_OF_PATTERNS]) 422 counter = 0; 423 } 424 return counter; 425 } 426 #endif 427 428 #if defined(CONFIG_SOFT_I2C) 429 void set_sda(int state) 430 { 431 I2C_ACTIVE; 432 I2C_SDA(state); 433 } 434 435 void set_scl(int state) 436 { 437 I2C_SCL(state); 438 } 439 440 int get_sda(void) 441 { 442 I2C_TRISTATE; 443 return I2C_READ; 444 } 445 446 int get_scl(void) 447 { 448 return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0; 449 } 450 #endif 451 452 #if defined(CONFIG_POST) 453 454 #define KM_POST_EN_L 44 455 #define POST_WORD_OFF 8 456 457 int post_hotkeys_pressed(void) 458 { 459 #if defined(CONFIG_KM_COGE5UN) 460 return kw_gpio_get_value(KM_POST_EN_L); 461 #else 462 return !kw_gpio_get_value(KM_POST_EN_L); 463 #endif 464 } 465 466 ulong post_word_load(void) 467 { 468 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF); 469 return in_le32(addr); 470 471 } 472 void post_word_store(ulong value) 473 { 474 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF); 475 out_le32(addr, value); 476 } 477 478 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 479 { 480 *vstart = CONFIG_SYS_SDRAM_BASE; 481 482 /* we go up to relocation plus a 1 MB margin */ 483 *size = CONFIG_SYS_TEXT_BASE - (1<<20); 484 485 return 0; 486 } 487 #endif 488 489 #if defined(CONFIG_SYS_EEPROM_WREN) 490 int eeprom_write_enable(unsigned dev_addr, int state) 491 { 492 kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state); 493 494 return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP); 495 } 496 #endif 497