1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2009 4 * Marvell Semiconductor <www.marvell.com> 5 * Prafulla Wadaskar <prafulla@marvell.com> 6 * 7 * (C) Copyright 2009 8 * Stefan Roese, DENX Software Engineering, sr@denx.de. 9 * 10 * (C) Copyright 2010 11 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 12 */ 13 14 #include <common.h> 15 #include <i2c.h> 16 #include <nand.h> 17 #include <netdev.h> 18 #include <miiphy.h> 19 #include <spi.h> 20 #include <asm/io.h> 21 #include <asm/arch/cpu.h> 22 #include <asm/arch/soc.h> 23 #include <asm/arch/mpp.h> 24 25 #include "../common/common.h" 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 /* 30 * BOCO FPGA definitions 31 */ 32 #define BOCO 0x10 33 #define REG_CTRL_H 0x02 34 #define MASK_WRL_UNITRUN 0x01 35 #define MASK_RBX_PGY_PRESENT 0x40 36 #define REG_IRQ_CIRQ2 0x2d 37 #define MASK_RBI_DEFECT_16 0x01 38 39 /* 40 * PHY registers definitions 41 */ 42 #define PHY_MARVELL_OUI 0x5043 43 #define PHY_MARVELL_88E1118_MODEL 0x0022 44 #define PHY_MARVELL_88E1118R_MODEL 0x0024 45 46 #define PHY_MARVELL_PAGE_REG 0x0016 47 #define PHY_MARVELL_DEFAULT_PAGE 0x0000 48 49 #define PHY_MARVELL_88E1118R_LED_CTRL_PAGE 0x0003 50 #define PHY_MARVELL_88E1118R_LED_CTRL_REG 0x0010 51 52 #define PHY_MARVELL_88E1118R_LED_CTRL_RESERVED 0x1000 53 #define PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB (0x7<<0) 54 #define PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT (0x3<<4) 55 #define PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK (0x0<<8) 56 57 /* I/O pin to erase flash RGPP09 = MPP43 */ 58 #define KM_FLASH_ERASE_ENABLE 43 59 60 /* Multi-Purpose Pins Functionality configuration */ 61 static const u32 kwmpp_config[] = { 62 MPP0_NF_IO2, 63 MPP1_NF_IO3, 64 MPP2_NF_IO4, 65 MPP3_NF_IO5, 66 MPP4_NF_IO6, 67 MPP5_NF_IO7, 68 MPP6_SYSRST_OUTn, 69 #if defined(KM_PCIE_RESET_MPP7) 70 MPP7_GPO, 71 #else 72 MPP7_PEX_RST_OUTn, 73 #endif 74 #if defined(CONFIG_SYS_I2C_SOFT) 75 MPP8_GPIO, /* SDA */ 76 MPP9_GPIO, /* SCL */ 77 #endif 78 MPP10_UART0_TXD, 79 MPP11_UART0_RXD, 80 MPP12_GPO, /* Reserved */ 81 MPP13_UART1_TXD, 82 MPP14_UART1_RXD, 83 MPP15_GPIO, /* Not used */ 84 MPP16_GPIO, /* Not used */ 85 MPP17_GPIO, /* Reserved */ 86 MPP18_NF_IO0, 87 MPP19_NF_IO1, 88 MPP20_GPIO, 89 MPP21_GPIO, 90 MPP22_GPIO, 91 MPP23_GPIO, 92 MPP24_GPIO, 93 MPP25_GPIO, 94 MPP26_GPIO, 95 MPP27_GPIO, 96 MPP28_GPIO, 97 MPP29_GPIO, 98 MPP30_GPIO, 99 MPP31_GPIO, 100 MPP32_GPIO, 101 MPP33_GPIO, 102 MPP34_GPIO, /* CDL1 (input) */ 103 MPP35_GPIO, /* CDL2 (input) */ 104 MPP36_GPIO, /* MAIN_IRQ (input) */ 105 MPP37_GPIO, /* BOARD_LED */ 106 MPP38_GPIO, /* Piggy3 LED[1] */ 107 MPP39_GPIO, /* Piggy3 LED[2] */ 108 MPP40_GPIO, /* Piggy3 LED[3] */ 109 MPP41_GPIO, /* Piggy3 LED[4] */ 110 MPP42_GPIO, /* Piggy3 LED[5] */ 111 MPP43_GPIO, /* Piggy3 LED[6] */ 112 MPP44_GPIO, /* Piggy3 LED[7], BIST_EN_L */ 113 MPP45_GPIO, /* Piggy3 LED[8] */ 114 MPP46_GPIO, /* Reserved */ 115 MPP47_GPIO, /* Reserved */ 116 MPP48_GPIO, /* Reserved */ 117 MPP49_GPIO, /* SW_INTOUTn */ 118 0 119 }; 120 121 static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; 122 123 #if defined(CONFIG_KM_MGCOGE3UN) 124 /* 125 * Wait for startup OK from mgcoge3ne 126 */ 127 static int startup_allowed(void) 128 { 129 unsigned char buf; 130 131 /* 132 * Read CIRQ16 bit (bit 0) 133 */ 134 if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0) 135 printf("%s: Error reading Boco\n", __func__); 136 else 137 if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16) 138 return 1; 139 return 0; 140 } 141 #endif 142 143 #if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352)) 144 /* 145 * All boards with PIGGY4 connected via a simple switch have ethernet always 146 * present. 147 */ 148 int ethernet_present(void) 149 { 150 return 1; 151 } 152 #else 153 int ethernet_present(void) 154 { 155 uchar buf; 156 int ret = 0; 157 158 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { 159 printf("%s: Error reading Boco\n", __func__); 160 return -1; 161 } 162 if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT) 163 ret = 1; 164 165 return ret; 166 } 167 #endif 168 169 static int initialize_unit_leds(void) 170 { 171 /* 172 * Init the unit LEDs per default they all are 173 * ok apart from bootstat 174 */ 175 uchar buf; 176 177 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { 178 printf("%s: Error reading Boco\n", __func__); 179 return -1; 180 } 181 buf |= MASK_WRL_UNITRUN; 182 if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { 183 printf("%s: Error writing Boco\n", __func__); 184 return -1; 185 } 186 return 0; 187 } 188 189 static void set_bootcount_addr(void) 190 { 191 uchar buf[32]; 192 unsigned int bootcountaddr; 193 bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR; 194 sprintf((char *)buf, "0x%x", bootcountaddr); 195 env_set("bootcountaddr", (char *)buf); 196 } 197 198 int misc_init_r(void) 199 { 200 #if defined(CONFIG_KM_MGCOGE3UN) 201 char *wait_for_ne; 202 u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE); 203 wait_for_ne = env_get("waitforne"); 204 205 if ((wait_for_ne != NULL) && (dip_switch == 0)) { 206 if (strcmp(wait_for_ne, "true") == 0) { 207 int cnt = 0; 208 int abort = 0; 209 puts("NE go: "); 210 while (startup_allowed() == 0) { 211 if (tstc()) { 212 (void) getc(); /* consume input */ 213 abort = 1; 214 break; 215 } 216 udelay(200000); 217 cnt++; 218 if (cnt == 5) 219 puts("wait\b\b\b\b"); 220 if (cnt == 10) { 221 cnt = 0; 222 puts(" \b\b\b\b"); 223 } 224 } 225 if (abort == 1) 226 printf("\nAbort waiting for ne\n"); 227 else 228 puts("OK\n"); 229 } 230 } 231 #endif 232 233 ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); 234 235 initialize_unit_leds(); 236 set_km_env(); 237 set_bootcount_addr(); 238 return 0; 239 } 240 241 int board_early_init_f(void) 242 { 243 #if defined(CONFIG_SYS_I2C_SOFT) 244 u32 tmp; 245 246 /* set the 2 bitbang i2c pins as output gpios */ 247 tmp = readl(MVEBU_GPIO0_BASE + 4); 248 writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , MVEBU_GPIO0_BASE + 4); 249 #endif 250 /* adjust SDRAM size for bank 0 */ 251 mvebu_sdram_size_adjust(0); 252 kirkwood_mpp_conf(kwmpp_config, NULL); 253 return 0; 254 } 255 256 int board_init(void) 257 { 258 /* address of boot parameters */ 259 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; 260 261 /* 262 * The KM_FLASH_GPIO_PIN switches between using a 263 * NAND or a SPI FLASH. Set this pin on start 264 * to NAND mode. 265 */ 266 kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1); 267 kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1); 268 269 #if defined(CONFIG_SYS_I2C_SOFT) 270 /* 271 * Reinit the GPIO for I2C Bitbang driver so that the now 272 * available gpio framework is consistent. The calls to 273 * direction output in are not necessary, they are already done in 274 * board_early_init_f 275 */ 276 kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1); 277 kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1); 278 #endif 279 280 #if defined(CONFIG_SYS_EEPROM_WREN) 281 kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38); 282 kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1); 283 #endif 284 285 #if defined(CONFIG_KM_FPGA_CONFIG) 286 trigger_fpga_config(); 287 #endif 288 289 return 0; 290 } 291 292 int board_late_init(void) 293 { 294 #if (defined(CONFIG_KM_COGE5UN) | defined(CONFIG_KM_MGCOGE3UN)) 295 u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE); 296 297 /* if pin 1 do full erase */ 298 if (dip_switch != 0) { 299 /* start bootloader */ 300 puts("DIP: Enabled\n"); 301 env_set("actual_bank", "0"); 302 } 303 #endif 304 305 #if defined(CONFIG_KM_FPGA_CONFIG) 306 wait_for_fpga_config(); 307 fpga_reset(); 308 toggle_eeprom_spi_bus(); 309 #endif 310 return 0; 311 } 312 313 int board_spi_claim_bus(struct spi_slave *slave) 314 { 315 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0); 316 317 return 0; 318 } 319 320 void board_spi_release_bus(struct spi_slave *slave) 321 { 322 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1); 323 } 324 325 #if (defined(CONFIG_KM_PIGGY4_88E6061)) 326 327 #define PHY_LED_SEL_REG 0x18 328 #define PHY_LED0_LINK (0x5) 329 #define PHY_LED1_ACT (0x8<<4) 330 #define PHY_LED2_INT (0xe<<8) 331 #define PHY_SPEC_CTRL_REG 0x1c 332 #define PHY_RGMII_CLK_STABLE (0x1<<10) 333 #define PHY_CLSA (0x1<<1) 334 335 /* Configure and enable MV88E3018 PHY */ 336 void reset_phy(void) 337 { 338 char *name = "egiga0"; 339 unsigned short reg; 340 341 if (miiphy_set_current_dev(name)) 342 return; 343 344 /* RGMII clk transition on data stable */ 345 if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®)) 346 printf("Error reading PHY spec ctrl reg\n"); 347 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, 348 reg | PHY_RGMII_CLK_STABLE | PHY_CLSA)) 349 printf("Error writing PHY spec ctrl reg\n"); 350 351 /* leds setup */ 352 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG, 353 PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT)) 354 printf("Error writing PHY LED reg\n"); 355 356 /* reset the phy */ 357 miiphy_reset(name, CONFIG_PHY_BASE_ADR); 358 } 359 #elif defined(CONFIG_KM_PIGGY4_88E6352) 360 361 #include <mv88e6352.h> 362 363 #if defined(CONFIG_KM_NUSA) 364 struct mv88e_sw_reg extsw_conf[] = { 365 /* 366 * port 0, PIGGY4, autoneg 367 * first the fix for the 1000Mbits Autoneg, this is from 368 * a Marvell errata, the regs are undocumented 369 */ 370 { PHY(0), PHY_PAGE, AN1000FIX_PAGE }, 371 { PHY(0), PHY_STATUS, AN1000FIX }, 372 { PHY(0), PHY_PAGE, 0 }, 373 /* now the real port and phy configuration */ 374 { PORT(0), PORT_PHY, NO_SPEED_FOR }, 375 { PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, 376 { PHY(0), PHY_1000_CTRL, NO_ADV }, 377 { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN }, 378 { PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST | 379 FULL_DUPLEX }, 380 /* port 1, unused */ 381 { PORT(1), PORT_CTRL, PORT_DIS }, 382 { PHY(1), PHY_CTRL, PHY_PWR_DOWN }, 383 { PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, 384 /* port 2, unused */ 385 { PORT(2), PORT_CTRL, PORT_DIS }, 386 { PHY(2), PHY_CTRL, PHY_PWR_DOWN }, 387 { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, 388 /* port 3, unused */ 389 { PORT(3), PORT_CTRL, PORT_DIS }, 390 { PHY(3), PHY_CTRL, PHY_PWR_DOWN }, 391 { PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, 392 /* port 4, ICNEV, SerDes, SGMII */ 393 { PORT(4), PORT_STATUS, NO_PHY_DETECT }, 394 { PORT(4), PORT_PHY, SPEED_1000_FOR }, 395 { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, 396 { PHY(4), PHY_CTRL, PHY_PWR_DOWN }, 397 { PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, 398 /* port 5, CPU_RGMII */ 399 { PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN | 400 FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX | 401 FULL_DPX_FOR | SPEED_1000_FOR }, 402 { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, 403 /* port 6, unused, this port has no phy */ 404 { PORT(6), PORT_CTRL, PORT_DIS }, 405 }; 406 #else 407 struct mv88e_sw_reg extsw_conf[] = {}; 408 #endif 409 410 void reset_phy(void) 411 { 412 #if defined(CONFIG_KM_MVEXTSW_ADDR) 413 char *name = "egiga0"; 414 415 if (miiphy_set_current_dev(name)) 416 return; 417 418 mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf, 419 ARRAY_SIZE(extsw_conf)); 420 mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR); 421 #endif 422 } 423 424 #else 425 /* Configure and enable MV88E1118 PHY on the piggy*/ 426 void reset_phy(void) 427 { 428 unsigned int oui; 429 unsigned char model, rev; 430 431 char *name = "egiga0"; 432 433 if (miiphy_set_current_dev(name)) 434 return; 435 436 /* reset the phy */ 437 miiphy_reset(name, CONFIG_PHY_BASE_ADR); 438 439 /* get PHY model */ 440 if (miiphy_info(name, CONFIG_PHY_BASE_ADR, &oui, &model, &rev)) 441 return; 442 443 /* check for Marvell 88E1118R Gigabit PHY (PIGGY3) */ 444 if ((oui == PHY_MARVELL_OUI) && 445 (model == PHY_MARVELL_88E1118R_MODEL)) { 446 /* set page register to 3 */ 447 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, 448 PHY_MARVELL_PAGE_REG, 449 PHY_MARVELL_88E1118R_LED_CTRL_PAGE)) 450 printf("Error writing PHY page reg\n"); 451 452 /* 453 * leds setup as printed on PCB: 454 * LED2 (Link): 0x0 (On Link, Off No Link) 455 * LED1 (Activity): 0x3 (On Activity, Off No Activity) 456 * LED0 (Speed): 0x7 (On 1000 MBits, Off Else) 457 */ 458 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, 459 PHY_MARVELL_88E1118R_LED_CTRL_REG, 460 PHY_MARVELL_88E1118R_LED_CTRL_RESERVED | 461 PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB | 462 PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT | 463 PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK)) 464 printf("Error writing PHY LED reg\n"); 465 466 /* set page register back to 0 */ 467 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, 468 PHY_MARVELL_PAGE_REG, 469 PHY_MARVELL_DEFAULT_PAGE)) 470 printf("Error writing PHY page reg\n"); 471 } 472 } 473 #endif 474 475 476 #if defined(CONFIG_HUSH_INIT_VAR) 477 int hush_init_var(void) 478 { 479 ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); 480 return 0; 481 } 482 #endif 483 484 #if defined(CONFIG_SYS_I2C_SOFT) 485 void set_sda(int state) 486 { 487 I2C_ACTIVE; 488 I2C_SDA(state); 489 } 490 491 void set_scl(int state) 492 { 493 I2C_SCL(state); 494 } 495 496 int get_sda(void) 497 { 498 I2C_TRISTATE; 499 return I2C_READ; 500 } 501 502 int get_scl(void) 503 { 504 return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0; 505 } 506 #endif 507 508 #if defined(CONFIG_POST) 509 510 #define KM_POST_EN_L 44 511 #define POST_WORD_OFF 8 512 513 int post_hotkeys_pressed(void) 514 { 515 #if defined(CONFIG_KM_COGE5UN) 516 return kw_gpio_get_value(KM_POST_EN_L); 517 #else 518 return !kw_gpio_get_value(KM_POST_EN_L); 519 #endif 520 } 521 522 ulong post_word_load(void) 523 { 524 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF); 525 return in_le32(addr); 526 527 } 528 void post_word_store(ulong value) 529 { 530 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF); 531 out_le32(addr, value); 532 } 533 534 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 535 { 536 *vstart = CONFIG_SYS_SDRAM_BASE; 537 538 /* we go up to relocation plus a 1 MB margin */ 539 *size = CONFIG_SYS_TEXT_BASE - (1<<20); 540 541 return 0; 542 } 543 #endif 544 545 #if defined(CONFIG_SYS_EEPROM_WREN) 546 int eeprom_write_enable(unsigned dev_addr, int state) 547 { 548 kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state); 549 550 return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP); 551 } 552 #endif 553