xref: /openbmc/u-boot/board/keymile/km_arm/km_arm.c (revision e89516f0)
1 /*
2  * (C) Copyright 2009
3  * Marvell Semiconductor <www.marvell.com>
4  * Prafulla Wadaskar <prafulla@marvell.com>
5  *
6  * (C) Copyright 2009
7  * Stefan Roese, DENX Software Engineering, sr@denx.de.
8  *
9  * (C) Copyright 2010
10  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
11  *
12  * See file CREDITS for list of people who contributed to this
13  * project.
14  *
15  * This program is free software; you can redistribute it and/or
16  * modify it under the terms of the GNU General Public License as
17  * published by the Free Software Foundation; either version 2 of
18  * the License, or (at your option) any later version.
19  *
20  * This program is distributed in the hope that it will be useful,
21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
23  * GNU General Public License for more details.
24  *
25  * You should have received a copy of the GNU General Public License
26  * along with this program; if not, write to the Free Software
27  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
28  * MA 02110-1301 USA
29  */
30 
31 #include <common.h>
32 #include <i2c.h>
33 #include <nand.h>
34 #include <netdev.h>
35 #include <miiphy.h>
36 #include <asm/io.h>
37 #include <asm/arch/kirkwood.h>
38 #include <asm/arch/mpp.h>
39 
40 #include "../common/common.h"
41 
42 DECLARE_GLOBAL_DATA_PTR;
43 
44 /* Multi-Purpose Pins Functionality configuration */
45 u32 kwmpp_config[] = {
46 	MPP0_NF_IO2,
47 	MPP1_NF_IO3,
48 	MPP2_NF_IO4,
49 	MPP3_NF_IO5,
50 	MPP4_NF_IO6,
51 	MPP5_NF_IO7,
52 	MPP6_SYSRST_OUTn,
53 	MPP7_PEX_RST_OUTn,
54 #if defined(CONFIG_SOFT_I2C)
55 	MPP8_GPIO,		/* SDA */
56 	MPP9_GPIO,		/* SCL */
57 #endif
58 #if defined(CONFIG_HARD_I2C)
59 	MPP8_TW_SDA,
60 	MPP9_TW_SCK,
61 #endif
62 	MPP10_UART0_TXD,
63 	MPP11_UART0_RXD,
64 	MPP12_GPO,		/* Reserved */
65 	MPP13_UART1_TXD,
66 	MPP14_UART1_RXD,
67 	MPP15_GPIO,		/* Not used */
68 	MPP16_GPIO,		/* Not used */
69 	MPP17_GPIO,		/* Reserved */
70 	MPP18_NF_IO0,
71 	MPP19_NF_IO1,
72 	MPP20_GPIO,
73 	MPP21_GPIO,
74 	MPP22_GPIO,
75 	MPP23_GPIO,
76 	MPP24_GPIO,
77 	MPP25_GPIO,
78 	MPP26_GPIO,
79 	MPP27_GPIO,
80 	MPP28_GPIO,
81 	MPP29_GPIO,
82 	MPP30_GPIO,
83 	MPP31_GPIO,
84 	MPP32_GPIO,
85 	MPP33_GPIO,
86 	MPP34_GPIO,		/* CDL1 (input) */
87 	MPP35_GPIO,		/* CDL2 (input) */
88 	MPP36_GPIO,		/* MAIN_IRQ (input) */
89 	MPP37_GPIO,		/* BOARD_LED */
90 	MPP38_GPIO,		/* Piggy3 LED[1] */
91 	MPP39_GPIO,		/* Piggy3 LED[2] */
92 	MPP40_GPIO,		/* Piggy3 LED[3] */
93 	MPP41_GPIO,		/* Piggy3 LED[4] */
94 	MPP42_GPIO,		/* Piggy3 LED[5] */
95 	MPP43_GPIO,		/* Piggy3 LED[6] */
96 	MPP44_GPIO,		/* Piggy3 LED[7], BIST_EN_L */
97 	MPP45_GPIO,		/* Piggy3 LED[8] */
98 	MPP46_GPIO,		/* Reserved */
99 	MPP47_GPIO,		/* Reserved */
100 	MPP48_GPIO,		/* Reserved */
101 	MPP49_GPIO,		/* SW_INTOUTn */
102 	0
103 };
104 
105 int ethernet_present(void)
106 {
107 	uchar	buf;
108 	int	ret = 0;
109 
110 	if (i2c_read(0x10, 2, 1, &buf, 1) != 0) {
111 		printf("%s: Error reading Boco\n", __func__);
112 		return -1;
113 	}
114 	if ((buf & 0x40) == 0x40)
115 		ret = 1;
116 
117 	return ret;
118 }
119 
120 int initialize_unit_leds(void)
121 {
122 	/*
123 	 * init the unit LEDs
124 	 * per default they all are
125 	 * ok apart from bootstat
126 	 * LED connected through BOCO
127 	 * BOCO	lies at the address  0x10
128 	 * LEDs are in the block CTRL_H	(addr 0x02)
129 	 * BOOTSTAT LED is the first 0x01
130 	 */
131 	#define BOCO        0x10
132 	#define CTRL_H      0x02
133 	#define APPLEDMASK  0x01
134 	uchar buf;
135 
136 	if (i2c_read(BOCO, CTRL_H, 1, &buf, 1) != 0) {
137 		printf("%s: Error reading Boco\n", __func__);
138 		return -1;
139 	}
140 	buf |= APPLEDMASK;
141 	if (i2c_write(BOCO, CTRL_H, 1, &buf, 1) != 0) {
142 		printf("%s: Error writing Boco\n", __func__);
143 		return -1;
144 	}
145 	return 0;
146 }
147 
148 int misc_init_r(void)
149 {
150 	char *str;
151 	int mach_type;
152 
153 	puts("Piggy:");
154 	if (ethernet_present() == 0)
155 		puts (" not");
156 	puts(" present\n");
157 
158 	str = getenv("mach_type");
159 	if (str != NULL) {
160 		mach_type = simple_strtoul(str, NULL, 10);
161 		printf("Overwriting MACH_TYPE with %d!!!\n", mach_type);
162 		gd->bd->bi_arch_number = mach_type;
163 	}
164 
165 	initialize_unit_leds();
166 
167 	return 0;
168 }
169 
170 int board_early_init_f(void)
171 {
172 	u32 tmp;
173 
174 	kirkwood_mpp_conf(kwmpp_config);
175 
176 	/*
177 	 * The FLASH_GPIO_PIN switches between using a
178 	 * NAND or a SPI FLASH. Set this pin on start
179 	 * to NAND mode.
180 	 */
181 	tmp = readl(KW_GPIO0_BASE);
182 	writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
183 	tmp = readl(KW_GPIO0_BASE + 4);
184 	writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
185 	printf("KM: setting NAND mode\n");
186 
187 #if defined(CONFIG_SOFT_I2C)
188 	/* init the GPIO for I2C Bitbang driver */
189 	kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
190 	kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
191 	kw_gpio_direction_output(KM_KIRKWOOD_SDA_PIN, 0);
192 	kw_gpio_direction_output(KM_KIRKWOOD_SCL_PIN, 0);
193 #endif
194 #if defined(CONFIG_SYS_EEPROM_WREN)
195 	kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
196 	kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
197 #endif
198 
199 	return 0;
200 }
201 
202 int board_init(void)
203 {
204 	/*
205 	 * arch number of board
206 	 */
207 	gd->bd->bi_arch_number = MACH_TYPE_KM_KIRKWOOD;
208 
209 	/* address of boot parameters */
210 	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
211 
212 	return 0;
213 }
214 
215 int last_stage_init(void)
216 {
217 	set_km_env();
218 	return 0;
219 }
220 
221 #if defined(CONFIG_CMD_SF)
222 int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
223 {
224 	u32 tmp;
225 	if (argc < 2)
226 		return cmd_usage(cmdtp);
227 
228 	if ((strcmp(argv[1], "off") == 0)) {
229 		printf("SPI FLASH disabled, NAND enabled\n");
230 		/* Multi-Purpose Pins Functionality configuration */
231 		kwmpp_config[0] = MPP0_NF_IO2;
232 		kwmpp_config[1] = MPP1_NF_IO3;
233 		kwmpp_config[2] = MPP2_NF_IO4;
234 		kwmpp_config[3] = MPP3_NF_IO5;
235 
236 		kirkwood_mpp_conf(kwmpp_config);
237 		tmp = readl(KW_GPIO0_BASE);
238 		writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
239 	} else if ((strcmp(argv[1], "on") == 0)) {
240 		printf("SPI FLASH enabled, NAND disabled\n");
241 		/* Multi-Purpose Pins Functionality configuration */
242 		kwmpp_config[0] = MPP0_SPI_SCn;
243 		kwmpp_config[1] = MPP1_SPI_MOSI;
244 		kwmpp_config[2] = MPP2_SPI_SCK;
245 		kwmpp_config[3] = MPP3_SPI_MISO;
246 
247 		kirkwood_mpp_conf(kwmpp_config);
248 		tmp = readl(KW_GPIO0_BASE);
249 		writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE);
250 	} else {
251 		return cmd_usage(cmdtp);
252 	}
253 
254 	return 0;
255 }
256 
257 U_BOOT_CMD(
258 	spitoggle,	2,	0,	do_spi_toggle,
259 	"En-/disable SPI FLASH access",
260 	"<on|off> - Enable (on) or disable (off) SPI FLASH access\n"
261 	);
262 #endif
263 
264 int dram_init(void)
265 {
266 	/* dram_init must store complete ramsize in gd->ram_size */
267 	/* Fix this */
268 	gd->ram_size = get_ram_size((volatile void *)kw_sdram_bar(0),
269 				kw_sdram_bs(0));
270 	return 0;
271 }
272 
273 void dram_init_banksize(void)
274 {
275 	int i;
276 
277 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
278 		gd->bd->bi_dram[i].start = kw_sdram_bar(i);
279 		gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i),
280 						       kw_sdram_bs(i));
281 	}
282 }
283 
284 /* Configure and enable MV88E1118 PHY */
285 void reset_phy(void)
286 {
287 	char *name = "egiga0";
288 
289 	if (miiphy_set_current_dev(name))
290 		return;
291 
292 	/* reset the phy */
293 	miiphy_reset(name, CONFIG_PHY_BASE_ADR);
294 }
295 
296 #if defined(CONFIG_HUSH_INIT_VAR)
297 int hush_init_var(void)
298 {
299 	ivm_read_eeprom();
300 	return 0;
301 }
302 #endif
303 
304 #if defined(CONFIG_BOOTCOUNT_LIMIT)
305 void bootcount_store(ulong a)
306 {
307 	volatile ulong *save_addr;
308 	volatile ulong size = 0;
309 	int i;
310 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
311 		size += gd->bd->bi_dram[i].size;
312 	}
313 	save_addr = (ulong*)(size - BOOTCOUNT_ADDR);
314 	writel(a, save_addr);
315 	writel(BOOTCOUNT_MAGIC, &save_addr[1]);
316 }
317 
318 ulong bootcount_load(void)
319 {
320 	volatile ulong *save_addr;
321 	volatile ulong size = 0;
322 	int i;
323 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
324 		size += gd->bd->bi_dram[i].size;
325 	}
326 	save_addr = (ulong*)(size - BOOTCOUNT_ADDR);
327 	if (readl(&save_addr[1]) != BOOTCOUNT_MAGIC)
328 		return 0;
329 	else
330 		return readl(save_addr);
331 }
332 #endif
333 
334 #if defined(CONFIG_SOFT_I2C)
335 void set_sda(int state)
336 {
337 	I2C_ACTIVE;
338 	I2C_SDA(state);
339 }
340 
341 void set_scl(int state)
342 {
343 	I2C_SCL(state);
344 }
345 
346 int get_sda(void)
347 {
348 	I2C_TRISTATE;
349 	return I2C_READ;
350 }
351 
352 int get_scl(void)
353 {
354 	return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0;
355 }
356 #endif
357 
358 #if defined(CONFIG_SYS_EEPROM_WREN)
359 int eeprom_write_enable(unsigned dev_addr, int state)
360 {
361 	kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state);
362 
363 	return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP);
364 }
365 #endif
366